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    30NOV2007 Search Results

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    LD1117-18

    Abstract: ld1117c LD1117 LD1117XX12 LD1117XX18 LD1117XX18C LD1117XX25 LD1117XX25C LD1117XX28 LD1117XX30
    Text: LD1117xx Low drop fixed and adjustable positive voltage regulators Features • Low dropout voltage 1 V typ. ■ 2.85 V device performances are suitable for SCSI-2 active termination ■ Output current up to 800 mA ■ Fixed output voltage of: 1.2 V, 1.8 V, 2.5 V,


    Original     		PDF LD1117xx O-220 OT-223 LD1117 LD1117-18 ld1117c LD1117XX12 LD1117XX18 LD1117XX18C LD1117XX25 LD1117XX25C LD1117XX28 LD1117XX30

    l30 sot 23

    Abstract: scsi electric diagram LD1117 date code LD1117S12CTR LD1117 LD1117XX12 LD1117XX18 LD1117XX18C LD1117XX25 LD1117XX25C
    Text: LD1117xx Adjustable and fixed low drop positive voltage regulator Features • Low dropout voltage 1 V typ. ■ 2.85 V device performances are suitable for SCSI-2 active termination ■ Output current up to 800 mA ■ Fixed output voltage of: 1.2 V, 1.8 V, 2.5 V,


    Original     		PDF LD1117xx O-220 OT-223 LD1117 l30 sot 23 scsi electric diagram LD1117 date code LD1117S12CTR LD1117XX12 LD1117XX18 LD1117XX18C LD1117XX25 LD1117XX25C

    dc to ac 400 hz

    Abstract: M665 M6651
    Text: M665 DUAL SAW, SELECTABLE FREQUENCY VCSO FOUT The M665 is a dual SAW, selectable frequency VCSO frequency source for low-jitter clock generation. An integrated SAW surface acoustic wave delay line implements the high-Q VCO (voltage controlled oscillator)


    Original     		PDF M665-01 M665-02 30Nov2007 dc to ac 400 hz M665 M6651

    tps51620

    Abstract: fds8884 tps51125 Inventec MPLC0730 AM4825P r5c804 TP889 hp d530 crb tps51125 kbc
    Text: www.laptop-schematics.com INVENTEC Preliminary Test 2008/03/25 EE DATE POWER DATE DRAWER DESIGN CHECK RESPONSIBLE DATE CHANGE NO. REV 3 SIZE = FILE NAME : XXXX-XXXXXX-XX P/N XXXXXXXXXXXX INVENTEC TITLE VER : Preliminary Test SIZE CODE A3 CS DOC. NUMBER REV


    Original     		PDF IEC951098 1-Nov-2007 tps51620 fds8884 tps51125 Inventec MPLC0730 AM4825P r5c804 TP889 hp d530 crb tps51125 kbc

    TI_BQ24721C_QFN_32P

    Abstract: D5036 tps51620 PowerPAD20 AM4825P tps51125 R1019 FM ic GMT_G680LT1_SOT23_5P pt10s TPS51620RHAR
    Text: INVENTEC PRELIMINARY TEST 07A99 2007 12 20 Pre-MP BUILD INVENTEC TITLE 07A99 Preliminary Test SIZE CODE A3 CHANGE by KOBE 23-Jan-2008 DOC. NUMBER REV X01 CS SHEET 1 OF 63 TABLE OF CONTENTS PAGE 1.COVER PAGE 2.INDEX 3.BLOCK DIAGRAM 4.POWER SEQUENCE BLOCK 5-12.SYSTEM POWER


    Original     		PDF 07A99 23-Jan-2008 R9033 R9034 AZ1015 C9038 C9040 R9039 TI_BQ24721C_QFN_32P D5036 tps51620 PowerPAD20 AM4825P tps51125 R1019 FM ic GMT_G680LT1_SOT23_5P pt10s TPS51620RHAR

    ld1117c

    Abstract: LD1117-33 LD1117
    Text: LD1117xx Low drop fixed and adjustable positive voltage regulators Features • Low dropout voltage 1 V typ. ■ 2.85 V Device performances are suitable for SCSI-2 active termination ■ Output current up to 800 mA ■ Fixed output voltage of: 1.2 V, 1.8 V, 2.5 V,


    Original     		PDF LD1117xx ld1117c LD1117-33 LD1117

    TFBGA105

    Abstract: M58PR512J JESD97 M39P0R9080E0 TFBGA-105 strataflash 512mbit
    Text: M39P0R9080E0 512 Mbit x16, Multiple Bank, Multi-Level, Burst Flash Memory 256 Mbit Low Power SDRAM, 1.8V Supply, Multi-Chip Package Feature summary • ■ Multi-Chip Package – 1 die of 512 Mbit (32Mb x 16, Multiple Bank, Multi-Level, Burst) Flash memory


    Original     		PDF M39P0R9080E0 TFBGA105 TFBGA105 M58PR512J JESD97 M39P0R9080E0 TFBGA-105 strataflash 512mbit

    TFBGA105

    Abstract: KF256 TFBGA-105 M39P0R8070E2 M58PR256J M58PR512J M65KA128AE A12-Amax
    Text: M39P0R8070E2 M39P0R9070E2 256 or 512Mbit x16, Multiple Bank, Multi-Level, Burst Flash memory 128 Mbit Low Power SDRAM, 1.8V supply, Multi-Chip Package Feature summary • Multi-Chip Package – 1 die of 256 (16Mb x 16) or 512 Mbit (32Mb x 16, Multiple Bank, Multi-Level, Burst)


    Original     		PDF M39P0R8070E2 M39P0R9070E2 512Mbit TFBGA105 64-bit TFBGA105 KF256 TFBGA-105 M39P0R8070E2 M58PR256J M58PR512J M65KA128AE A12-Amax

    LD1117-33

    Abstract: LD1117-18 ld1117c LD1117S33TR LD1117 date code LD1117 ST 330 LD1117DT18TR LD1117S12CTR LD1117 LD1117XX12
    Text: LD1117xx Low drop fixed and adjustable positive voltage regulators Features • Low dropout voltage 1 V typ. ■ 2.85 V Device performances are suitable for SCSI-2 active termination ■ Output current up to 800 mA ■ Fixed output voltage of: 1.2 V, 1.8 V, 2.5 V,


    Original     		PDF LD1117xx O-220 OT-223 LD1117 LD1117-33 LD1117-18 ld1117c LD1117S33TR LD1117 date code LD1117 ST 330 LD1117DT18TR LD1117S12CTR LD1117XX12

    Untitled

    Abstract: No abstract text available
    Text: PCI1512 www.ti.com SLLA231 – JUNE 2006 CardBus Controller FEATURES • • • • • • • • A 216-Terminal MicroStar BGA PBGA GVF/ZVF Package 2.5-V Core Logic and 3.3-V I/O with Universal PCI Interfaces Compatible with 3.3-V and 5-V PCI Signaling Environments


    Original     		PDF PCI1512 SLLA231 216-Terminal 16-Bit TPS2211A

    Untitled

    Abstract: No abstract text available
    Text: TPS3613Ć01 www.ti.com SLVS340C − DECEMBER 2000 − REVISED NOVEMBER 2007 ADJUSTABLE BATTERĆBACKUP SUPERVISOR FOR RAM RENTENTION FEATURES D Supply Current of 40 µA Max D Battery Supply Current of 100 nA (Max) D Supply Voltage Supervision Range: DESCRIPTION


    Original     		PDF TPS361301 SLVS340C 100-ms TPS3613-01

    str 5 q 0765 POWER SUPPLY CIRCUIT

    Abstract: No abstract text available
    Text: TPS51116 www.ti.com SLUS609F – DECEMBER 2007 – REVISED DECEMBER 2008 COMPLETE DDR, DDR2 AND DDR3 MEMORY POWER SOLUTION SYNCHRONOUS BUCK CONTROLLER, 3-A LDO, BUFFERED REFERENCE FEATURES 1 DESCRIPTION • Synchronous Buck Controller VDDQ – Wide-Input Voltage Range: 3.0-V to 28-V


    Original     		PDF TPS51116 SLUS609F TPS51116 DDR2/SSTL-18, 400kHz str 5 q 0765 POWER SUPPLY CIRCUIT

    Untitled

    Abstract: No abstract text available
    Text: CDCM7005 www.ti.com SCAS793C – JUNE 2005 – REVISED DECEMBER 2007 3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER FEATURES 1 • GND GND GND GND GND C VBB GND AVCC AVCC AVCC AVCC AVCC GND STATUS_ REF or PRI_SEC_ CLK STATUS_ D VCXO_IN GND GND


    Original     		PDF CDCM7005 SCAS793C

    Untitled

    Abstract: No abstract text available
    Text: LD1117xx Adjustable and fixed low drop positive voltage regulator Features • Low dropout voltage 1 V typ. ■ 2.85 V device performances are suitable for SCSI-2 active termination ■ Output current up to 800 mA ■ Fixed output voltage of: 1.2 V, 1.8 V, 2.5 V,


    Original     		PDF LD1117xx LD1117 OT-223 O-220

    TPS51116

    Abstract: IRF7821 IRF7832 SSTL-18 TPS51116PWP TPS51116RGE
    Text: TPS51116 www.ti.com SLUS609F – DECEMBER 2007 – REVISED DECEMBER 2008 COMPLETE DDR, DDR2 AND DDR3 MEMORY POWER SOLUTION SYNCHRONOUS BUCK CONTROLLER, 3-A LDO, BUFFERED REFERENCE FEATURES 1 DESCRIPTION • Synchronous Buck Controller VDDQ – Wide-Input Voltage Range: 3.0-V to 28-V


    Original     		PDF TPS51116 SLUS609F 100-ns TPS51116 IRF7821 IRF7832 SSTL-18 TPS51116PWP TPS51116RGE

    PSRAM

    Abstract: M36P0R9060E0 M58PR512J M69KB096AM M58PRxxxJ
    Text: M36P0R9060E0 512 Mbit x16, Multiple Bank, Multi-Level, Burst Flash memory 64 Mbit (Burst) PSRAM, 1.8V supply, Multi-Chip Package Feature summary • ■ Multi-Chip Package – 1 die of 512 Mbit (32Mb x 16, Multiple Bank, Multi-Level, Burst) Flash memory


    Original     		PDF M36P0R9060E0 TFBGA107 108MHz, 66MHz PSRAM M36P0R9060E0 M58PR512J M69KB096AM M58PRxxxJ

    Untitled

    Abstract: No abstract text available
    Text: CDCM7005 www.ti.com SCAS793C – JUNE 2005 – REVISED DECEMBER 2007 3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER FEATURES 1 • GND GND GND GND GND C VBB GND AVCC AVCC AVCC AVCC AVCC GND STATUS_ REF or PRI_SEC_ CLK STATUS_ D VCXO_IN GND GND


    Original     		PDF CDCM7005 SCAS793C

    LD1117DT33TR

    Abstract: LD1117S33TR LD1117D12C
    Text: LD1117xx Adjustable and fixed low drop positive voltage regulator Features • Low dropout voltage 1 V typ. ■ 2.85 V device performances are suitable for SCSI-2 active termination ■ Output current up to 800 mA ■ Fixed output voltage of: 1.2 V, 1.8 V, 2.5 V,


    Original     		PDF LD1117xx LD1117 OT-223 O-220 LD1117DT33TR LD1117S33TR LD1117D12C

    tps51620

    Abstract: pt10s TPS51620RHAR W775L fds8884 INVENTEC R5C804 tps51125 63A43 Sil1392
    Text: INVENTEC Preliminary Test 2008/03/25 EE DRAWER DESIGN CHECK RESPONSIBLE SIZE = 3 XXXX-XXXXXX-XX P/N NAME XXXXXXXXXXXX FILE : DATE CHANGE NO. REV DATE DATE POWER INVENTEC TITLE VER : PT10SC DOC. NUMBER A3 CODE SIZE CS Model_No SHEET OF 1 63 REV X01 TABLE OF CONTENTS


    Original     		PDF PT10SC PT10SC IEC951098 1-Nov-2007 tps51620 pt10s TPS51620RHAR W775L fds8884 INVENTEC R5C804 tps51125 63A43 Sil1392

    T1T7

    Abstract: No abstract text available
    Text: CDCE421 www.ti.com SCAS842A – APRIL 2007 – REVISED DECEMBER 2007 Fully Integrated Wide-Range, Low-Jitter, Crystal-Oscillator Clock Generator • FEATURES 1 • • • • • • • Single 3.3-V Supply High-Performance Clock Generator Incorporating Crystal-Oscillator Circuitry With


    Original     		PDF CDCE421 SCAS842A 10-kHz 10-MHz T1T7

    QFN-24 footprint

    Abstract: No abstract text available
    Text: CDCE421 www.ti.com SCAS842A – APRIL 2007 – REVISED DECEMBER 2007 Fully Integrated Wide-Range, Low-Jitter, Crystal-Oscillator Clock Generator • FEATURES 1 • • • • • • • Single 3.3-V Supply High-Performance Clock Generator Incorporating Crystal-Oscillator Circuitry With


    Original     		PDF CDCE421 SCAS842A 10-kHz 10-MHz QFN-24 footprint

    Untitled

    Abstract: No abstract text available
    Text: CDCM7005 www.ti.com SCAS793C – JUNE 2005 – REVISED DECEMBER 2007 3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER FEATURES 1 • GND GND GND GND GND C VBB GND AVCC AVCC AVCC AVCC AVCC GND STATUS_ REF or PRI_SEC_ CLK STATUS_ D VCXO_IN GND GND


    Original     		PDF CDCM7005 SCAS793C

    Burr-Brown IC data book appendix c INA125

    Abstract: No abstract text available
    Text: INA 125 INA125 INA1 25 INSTRUMENTATION AMPLIFIER With Precision Voltage Reference FEATURES APPLICATIONS ● LOW QUIESCENT CURRENT: 460µA ● PRECISION VOLTAGE REFERENCE: 1.24V, 2.5V, 5V or 10V ● SLEEP MODE ● LOW OFFSET VOLTAGE: 250µV max ● PRESSURE AND TEMPERATURE BRIDGE


    Original     		PDF INA125 100dB 16-PIN SO-16 VREF10 Burr-Brown IC data book appendix c INA125

    Untitled

    Abstract: No abstract text available
    Text: 4 T H IS D R A W IN G C O P Y R IG H T IS 2 U N P U B L IS H E D . 1979 BY ^ C O RELEASED E L E C T R O N IC S C O R P O R A T IO N . FO R ALL P U B L IC A T IO N R IG H T S JAN 1979. R E V IS IO N S RESERVED. LTR D E S C R IP T IO N D R EV ISE D DATE A PVD


    OCR Scan     		PDF 30NOV2007 12POS