30811 Search Results

Contextual Info: 1 — UJ LU <*o — FSA 308119 CO COLORE: GIALLO COLOUR: YELLOW MATERIALE: PBT n a i u r a l e MATERIAL: PBT Description : C o n n e t t o r e Portafemmine a 2 v i e AIR-BAG De s tr o Female H o l d e r r i g h t P o l a r i z a t i o n Draft iB/F"'. This is our exclusive property.

Contextual Info: InnovativeInnov Innovative VCSEL Solutions . Delivered Advanced Optical Components 2.5Gbps 850nm PIN + Preamp with RSSI TO-46 Package HFD3081-103 Key Features: • • • • • • • TO-46 hermetic package Data rates from 155 Mbps to 2.5 Gbps GaAs PIN detector

Contextual Info: CY7C1319KV18/CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth

Contextual Info: CY7C1163KV18/CY7C1165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • Separate independent read and write data ports

Contextual Info:  CY7C1143KV18/CY7C1145KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.0 Cycle Read Latency 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • Separate independent read and write data ports

30021

Abstract: L48C L41C IC L44C DATASHEET L30C l31c L43C ORSO42G5 ORSO82G5 ORT42G5
Contextual Info: ORCA ORSO42G5 and ORSO82G5 0.6 - 2.7 Gbps SONET Backplane Interface FPSCs August 2005 Data Sheet Introduction Lattice has extended its family of high-speed serial backplane devices with the ORSO42G5 and ORSO82G5 devices. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSO42G5 and

D2326

Abstract: zener 150mW 2.7V smd zener diode color code Zener diode 8,2v SMX3200 FDC6420C equivalent USB2I2C SMB120 zener diode 6.8v smd diode U 34 C83
Contextual Info: Revision G SMB120 Evaluation Kit Quick-Start User’s Guide SMB120EV General Description The SMB120EVAL kit is a fully functional printed circuit board designed to demonstrate all the features of the SMB120 Nonvolatile, 9-Ch Programmable DC/DC converter with integrated power management. The

Contextual Info: temperature sensors infrared sensor M18TIP8Q • connection via M12 x 1 connector ■ D:S ratio 8:1 ■ Operating voltage 12…30 VDC ■ Measuring range adjustable via teach-in ■ Analog output 4.20 mA ■ PNP Alarm output switches at 20 mA ■ Temperature range 0 … +300 °C

7002A

Abstract: LDML30811SRC
Contextual Info: NO.：QB/SPS 73 PS 7002A SPECIFICATIONS NAME: TYPE: Φ7.62 LAMP DOT MATRIX 30811SRC SHENZHEN DITELONG INDUSTRIAL CO.,LTD. SHENZHEN CANDELA ELECTRONIC CO.,LTD. SHENZHEN SUCCESS PHOTOELECTRONICS CO.,LTD SHENZHEN OFFICE Add: Room 1911,Zhongwin Science & Techn.Bldg,Bagua 3th Rd.Bagualing Industry Zone Shenzhen,China

HFD3081-108

Abstract: HFD PIN photodiode 850 nm NEP HFD3081 HFD PIN photodiode 850 nm pin photodiode 1550nm sensitivity 10gbps HFD 3081 850NM fiber optics ADVANCED COMMUNICATION system pin photodetector 2.5Gbps led 850nm 155mbps
Contextual Info: DATA SHEET 2.5GBPS 850NM PIN + PREAMP TO-46 PACKAGE HFD3081-108 FEATURES: Low electrical parasitic TO-46 package The HFD3081-108 use a high-performance GaAs PIN photo-detector packaged with a transimpedance amplifier designed to meet performance requirements

3-42-102

Abstract: 220325 30.4-112 31-0102 303-102
Contextual Info: Variable Attenuators and Phase Shifters 18-325 GHz 3 WG 103/112 Series Dial Variable Phase Shifter Features • ■ ■ ■ 0 ‘ -180" Phase Shift Accurate Repeatability Minimum Insertion Loss Frequency C alibration Available Description Variable w aveguide phase shifters provide a sim ple and con­

Contextual Info: AP Version: AP, Language: en Solar inverters for Asia-Pacific from Delta The heart of your PV system Content About us 1 Product overview 1 SOLIVIA - Solar inverters for Asia-Pacific 2 String inverters with transformer 2 Modular central inverters 12 Block inverters

NS250H

Abstract: NS160H NSX100H Schneider NSX 400 F NS100N NS100H MA NS250N NSX100 NS160N NSX100F
Contextual Info: Low Voltage Compact NSX100 to 630 Circuit breakers and switch-disconnectors Substitution guide - Technical characteristics 2010 Substitution guide Technical characteristics Performance levels and trip units 2 Compact NS100/160/250 Compact NSX100/160/250 Compact NS400/630

Contextual Info: temperature sensors infrared sensor M18TIP8 • connection via cable, 2 m ■ D:S ratio 8:1 ■ Operating voltage 12…30 VDC ■ Measuring range adjustable via teach-in ■ Analog output 4.20 mA ■ PNP Alarm output switches at 20 mA ■ Temperature range 0 … +300 °C

C502 Zener diode

Abstract: vr301 potentiometer VR501 F101 Type T fuse TRANSISTOR C309 4518BE VR502 vr302 potentiometer 2sc1015-GR 2SC1015GR
Contextual Info: ^ SERVICING INFORMATION B X PRECISION* M O D E L 3011A 3011B FUNCTION GENERATOR PARTS LIST SCHEMATIC SYMBOL DESCRIPTION B+K PRECISION PART NUMBER RESISTORS Unlisted resistors are +5%, 1/4 W. See Schematic for value. R101, 102 R104 R105 R205 R206 R207 R208

AD30102

Abstract: E3P15
Contextual Info: ORCA ORT42G5 and ORT82G5 06 to 3.7 Gbits/s XAUI and FC FPSCs March 2004 Data Sheet Introduction Lattice Semiconductor has developed a family of next generation FPSCs intended for high-speed serial backplane data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the

ORCA ORT42G5

Contextual Info: ORCA ORT42G5 and ORT82G5 3.7 Gbits/s XAUI and 4.25 Gbits/s FC FPSCs November 2003 Data Sheet Introduction Lattice Semiconductor has developed a family of next generation FPSCs intended for high-speed serial backplane data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the

3M Touch Systems

Contextual Info:  CY7C1143KV18, CY7C1145KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.0 Cycle Read Latency 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • Separate independent read and write data ports

AL437

Abstract: L97c L235C L103T L41C L140C L94C l165c L239C L43C
Contextual Info: ORCA ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC November 2003 Preliminary Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSPI4 FPSC contains two

L67c

Abstract: L41C l44c L71C l75c transistor l57c IC L44C DATASHEET l31c L47c l51c
Contextual Info: ORCA ORT42G5 and ORT82G5 06 to 3.7 Gbits/s XAUI and FC FPSCs February 2004 Data Sheet Introduction Lattice Semiconductor has developed a family of next generation FPSCs intended for high-speed serial backplane data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the

l37c 8 pin

Abstract: L41C G40TL l34c L43C L74c L18T l14c L25C ENCODER l31c
Contextual Info: ORCA ORT42G5 and ORT82G5 0.6 to 3.7 Gbps XAUI and FC FPSCs July 2008 Data Sheet DS1027 Introduction Lattice Semiconductor has developed a family of next generation FPSCs intended for high-speed serial backplane data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the

schematic diagram atx Power supply 500w

Abstract: pioneer PAL 012A 1000w inverter PURE SINE WAVE schematic diagram 600va numeric ups circuit diagrams winbond bios 25064 TLE 9180 infineon smsc MEC 1300 nu TBE schematic diagram inverter 2000w DK55 circuit diagram of luminous 600va UPS
Contextual Info: QUICK INDEX NEW IN THIS ISSUE! Detailed Index - See Pages 3-24 Digital Signal Processors, iCoupler , iMEMS® and iSensor . . . . . 805, 2707, 2768-2769 Connectors, Cable Assemblies, IC Sockets . . . . . . . . . . . 28-568 RF Connectors . . . . . . . . . . . . . . . . . . . . . . Pages 454-455

CY7C1145KV18

Contextual Info:  CY7C1141KV18, CY7C1156KV18 CY7C1143KV18, CY7C1145KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.0 Cycle Read Latency Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions With Read Cycle Latency of 2.0 cycles:

TL 2272 DECODER

Abstract: 10G BERT TL 2262 L36CA 30132 verilog code 16 bit LFSR in PRBS 10gbps serdes 30014 ap13.6 diode 680-pin
Contextual Info: Data Sheet April, 2002 ORCA ORT82G5 1.0—1.25/2.0—2.5/3.125—3.5 Gbits/s 8b/10b SERDES Backplane Interface FPSC Introduction Lattice has developed a next generation FPSC intended for high-speed serial backplane data transmission. Built on the Series 4 reconfigurable embedded system-on-chips SoC architecture, the