304WORD Search Results

Contextual Info: TMS44100, TMS44100P 4194304-BIT DYNAMIC RANDOM-ACCESS MEMORY SMHS410F-SEPTEMBER 1989-REVISED DECEMBER 1992 Single 5-V Power Supply ±10% Tolerance Performance Ranges: ACCESS ACCESS ACCESS SD P AC K A G E t (TOP VIEW) DJ P A C K A G E t (TOP VIEW) Organization . . . 4194 304 x 1

Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT /¿PD4216400,4217400 16 M-BIT DYNAMIC RAM 4 M-WORD BY 4-BIT, FAST PAGE MODE Description The /JPD4216400, 4217400 are 4 194 304 w o rd s by 4 bits d yn a m ic CMOS RAMs. These d iffe r in refresh cycle. These are packed in 26-pin plastic TSOP II and 26-pin plastic SOJ.

ic 4194 notes with IC diagram

Abstract: RAS24
Contextual Info: SMJ417400 4 194 304-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS044-NQVEMBER 1992 Organization . . . 4 194 304 FNC PA C K A G Et 4 x TO P V IE W Single 5-V Power Supply (10% Tolerance) VCC D NC W RAS A11 Performance Ranges: READ ACCESS AC CESS ACCESS

TM497EU9

Abstract: TMS417400DJ simm 30-pin 9-bit 30 pin 9-bit simm memory 30-pin simm memory 30-pin SIMM 30-pin 9-bit ram module SIMM 30-pin
Contextual Info: TM497EU9 4194304-WORD BY 9-BIT DYNAMIC RAM MODULE f ♦ s S M M S 49 9- FEBRUARY 1994 Organization . . . 41943 04 x 9 U SINGLE-IN-LINE PACKAGE TOP VIEW Single 5-V Power Supply (±10% Tolerance) 30-Pin Single-In-Line Memory Module (SIMM) for Use W ith Sockets

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT F/ iPD42S16400L, 4216400L, 42S17400L, 4217400L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 4 M-WORD BY 4-BIT, FAST PAGE MODE a DESCRIPTION The /¿PD42S16400L, 4216400L, 42S17400L, 4217400L are 4 194 304 words by 4 bits dynamic CMOS RAMs.

nec 4217400

Abstract: 4217400 upd4217400
Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT juPD4216400,4217400 16 M-BIT DYNAMIC RAM 4 M-WORD BY 4-BIT, FAST PAGE MODE Description The ¿ PD4216400, 4217400 are 4 194 304 w o rd s by 4 b its d yn a m ic CMOS RAMs. These d iffe r in refresh cycle. These are packed in 26-pin plastic TSOP (II and 26-pin plastic SOJ.

Contextual Info: SMJ44100 4194 304-WORD BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS040B-JANUARY 1991-REVISED JULY 1991 JD PACKAGET TOP VIEW Processed to MIL-STD-883, Class B Military Temperature Range. . . -5 5 °C to 125°C D C w C Organization . . . 4 194 304 x 1 Performance Ranges:

Contextual Info: TMS46100, TMS46100P 4194 304-WORD BY 1-BIT LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES SMHS461-DECEMBER 1992 ACCESS ACCESS ACCESS TIME ‘ RAC (MAX) TMS46100/P-70 * * * * * * * * READ TIME TIME OR WRITE (tCAC) (MAX) (tAA) (MAX) CYCLE (MIN) 130 ns 70 ns 18 ns

Contextual Info: TMS417400 4194 304-WDRD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS740A-JULY 1991-REVISED DECEMBER 1992 This data sheet is applicable to all TMS417400s symbolized with Revision “A " and subsequent revisions as described on page 23. V CC : 1 DQ1 c 2 DQ2 c 3

Contextual Info: SMJ44100 4 194 304-WORD BY 1 BIT DYNAMIC RANDOM-ACCESS MEMORY S G M S 0 4 Q — J A N U A R Y 1991 MIL-STD-883C, Class B, High-Reliablllty Processing JD Package Top View x 1 18 2 3 17 A0 : A1 A2 : A3 5 15 14 6 13 7 12 c c 1 Single 5-V Power Supply (±10% Tolerance)

777T7

Contextual Info: NEC MOS INTEGRATED CIRCUIT / ¿P D 4 2 1 6 4 0 5 16 M-BIT DYNAMIC RAM 4 M-WORD BY 4-BIT, HYPER PAGE MODE DESCRIPTION The /iPD4216405 is a 4 194 304 words by 4 bits dynamic CMOS RAM with optional hyper page mode. Hyper page mode is a kind of the page mode and is useful for the read operation.

Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT ju P D 4 2 S 1 6 4 0 5 L , 4 2 1 6 4 0 5 L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 4 M-WORD BY 4-BIT, HYPER PAGE MODE DESCRIPTION The //PD42S16405L, 4216405L are 4 194 304 words by 4 bits dynamic CMOS RAMs with optional hyper page

Contextual Info: IS42S46400A 4-bank x 16,777,216 - word x 4-bit IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) ISSI 256 Mb Synchronous DRAM AUGUST 2004 DESCRIPTION IS42S46400A is organized as 4-bank x 16,777,216-word x 4-bit Synchronous DRAM with LVTTL interface and

42S17405

Contextual Info: PRELIMINARY DATA SHEET CMOS INTEGRATED CIRCUIT ju P D 4 2 S 1 7 4 0 5 , 4 2 1 7 4 0 5 16 M BIT DYNAMIC RAM 4 M-WORD BY 4-BIT, HYPER PAGE MODE Description The /iPD42S17405, 4217405 are 4 194 304 w o rd s by 4 bits CMOS d yn a m ic R AM s w ith o p tio n a l h y p e r page

4194

Abstract: 3A414 A10C tms417400
Contextual Info: TMS41610016 777 216-BIT TMS416400 4194 304-WORD BY 4-BIT TMS417400 4194 304-WORD BY 4-BIT DYNAMIC RANDOM ACCESS MEMORIES SMKS003-DECEMBER 1992 3-State Unlatched Output This Product Preview is Applicable to All TMS416100/P, TMS416400/P, and TMS417400/P Devices Symbolized With

Contextual Info: TMS416400 4194 304-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY REV A — SMKS640 — JANUARY 1991 DZ Package T o p V ie w < o o Single 5-V Power Supply (10% Tolerance) Performance Ranges: ACCESS ACCESS ACCESS READ TIME TIME TIME OR WRITE tRAC *CAC *AA CYCLE

TMS44100DJ

Contextual Info: TM497EAD9B 4 194 304-WQRD BY 9-BIT DYNAMIC RAM MODULE S M M S 4 7 9 -D E C E M B E R 1992 Organization. . . 4194 304 x 9 AO SINGLE-IN-LINE P AC KA G Et TOP VIEW 30-Pin Single In-Line Memory Module (SIMM) for Use With Sockets V cc CAS DQ1 A0 A1 DQ2 A2 A3

ras 0910

Abstract: 30021
Contextual Info: SMJ44100 4 194 304-WORD BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY S G M S 040S — JANUARY 1991 — R E VIS ED JULY 1991 MIL-STD-883C, Class B, High-Reliability Processing JD Package Top View Military Temperature Range . . . - 55°C to 125°C D W RAS Organization . . . 4 194 304 x 1

Contextual Info: IS42S46400A 4-bank x 16,777,216 - word x 4-bit IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) ISSI 256 Mb Synchronous DRAM AUGUST 2004 DESCRIPTION IS42S46400A is organized as 4-bank x 16,777,216-word x 4-bit Synchronous DRAM with LVTTL interface and

nec 424100

Abstract: PD424100-70L
Contextual Info: NEC MOS INTEGRATED CIRCUIT juPD424100, 424100-L 4 M-BIT DYNAMIC RAM 4 M-WORD BY 1-BIT, FAST PAGE MODE Description The /iPD424100, 424100-L are 4 194 304 words by 1 bit dynamic CMOS RAMs. The fast page mode capability realize high speed access and low power consumption.

p2v56s

Contextual Info: 256Mb Synchronous DRAM Specification P2V56S20BTP P2V56S30BTP P2V56S40BTP Deutron Electronics Corp. 8F, 68, SEC. 3, NANKING E. RD., TAIPEI 104, TAIWAN, R. O. C. TEL : 886-2-2517-7768 FAX : 886-2-2517-4575 http: // www.deutron.com.tw 256Mb Synchronous DRAM 256Mb Synchronous DRAM

upd424100

Abstract: d424100 upd424100la nec vw rcd 300 nec 424100 UPD424100GS
Contextual Info: F L.427525 DGHlfil? 301 H N E C E AT A SHEET NEC MOS INTEGRATED CIRCUIT PD424100 4 M-BIT DYNAMIC RAM 4 M-WORD BY 1-BIT, FAST PAGE MODE DESCRIPTION The //PD424100 ¡s a 4 194 304 w ords by 1 bit dynam ic CMOS RAM. The fast page mode capability realize high speed access and low power consum ption.

Contextual Info: IS42S46400A 4-bank x 16,777,216 - word x 4-bit IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) ISSI 256 Mb Synchronous DRAM AUGUST 2004 DESCRIPTION IS42S46400A is organized as 4-bank x 16,777,216-word x 4-bit Synchronous DRAM with LVTTL interface and

Contextual Info: IS42S46400A 4-bank x 16,777,216 - word x 4-bit IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) ISSI 256 Mb Synchronous DRAM AUGUST 2004 DESCRIPTION IS42S46400A is organized as 4-bank x 16,777,216-word x 4-bit Synchronous DRAM with LVTTL interface and