80X86
Abstract: AD10 AD11 AD12 ECMA-102
Text: MATRA MHS 29C95 Multi-Channel ECMA 102/V110 Protocol Controller Description The MHS 29C95 is a multi-channel data link protocol controlller device. It multiplexes/demultiplexes up to 32 full duplex data channels to support implementation of data links based on either the ECMA 102/V110 protocol
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29C95
102/V110
29C95
29C3XX
29C96
ei9C95
80X86
AD10
AD11
AD12
ECMA-102
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One-chip telephone IC
Abstract: telephone line voice amplifier Voice to e1 converter circuit U 4076 One-chip telephone cordless IC VN2410* mosfet BFP67 slc96 remote terminal E1 PCM encoder V30 CPU
Text: TEMIC Semiconductors Communication Segment Digital Networks Wireless Communication Wired Communication Communication We’ve been supporting advances in communications industry for decades. Today, we continue to offer the best combination of applications knowledge and leading-edge solutions required by the
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29C93A
102/V
V25bis)
PQFP44
29C93A
29C921
80C51
One-chip telephone IC
telephone line voice amplifier
Voice to e1 converter circuit
U 4076
One-chip telephone cordless IC
VN2410* mosfet
BFP67
slc96 remote terminal
E1 PCM encoder
V30 CPU
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ITR17
Abstract: ITR24 80X86 AD10 AD11 AD12 AD14 ITR28
Text: 29C94 MATRA MHS Multi-Channel HDLC Protocol Controller Description The MHS 29C94 is a multi channel data link protocol controller device. It multiplexes/demultiplexes up to 32 full duplex data channels to support implementation of high speed data links based on either HDLC protocol or
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29C94
29C94
ITR17
ITR24
80X86
AD10
AD11
AD12
AD14
ITR28
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M-TRON HC49
Abstract: HC49 MSC1311
Text: 29C318 MATRA MHS E1 NIU / ISDN PRI Transceiver Description The 29C318 is the first fully integrated transceiver for E1 NIU and ISDN Primary Rate Interface ISDN PRI applications at 2.048 MHz. This transceiver operates over 2 km of 0.4 mm twisted-pair cable without any
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29C318
29C318
29C3XX
29C300
29C301
29C304
29C305
M-TRON HC49
HC49
MSC1311
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mxt 211
Abstract: signalling and frame alignment in E1 G704 SLC96 alarm frame format b30 c300 - 1 tsr1-24
Text: 29C96 MATRA MHS T1-DS1/E1-CEPT Framer Formatter Description The 29C96 is a programmable CMOS device interfacing with T1-DS1 or E1-CEPT transceivers. The 29C96 supports following frame formats : D DS1 : 4 frames DMI , D4 (G704), ESF (G704), SLC-96 (DMI), DDS (DMI)
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29C96
29C96
SLC-96
29C94
mxt 211
signalling and frame alignment in E1
G704
SLC96 alarm frame format
b30 c300 - 1
tsr1-24
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29C94
Abstract: ANM036 line E1 e1-t1
Text: ANM036 MATRA MHS Connecting 29C96 and 29C94 Introduction The 29C94 and 29C96 are parts of MHS's ISDN primary rate chipset. The 29C94 is a multichannel HDLC controller and the 29C96 is a framer with time slots switching capabilities. These two components can be used in T1-DS1 1.544MHz or E1-CEPT
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ANM036
29C96
29C94
29C94
544MHz)
048MHz)
29C3xx
ANM036
line E1
e1-t1
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1000H
Abstract: 106B ANM035 TS16 mcr 106B
Text: ANM035 MATRA MHS Programming E1-CEPT modes of the 29C96 Introduction The MHS's 29C96 is a complete T1-DS1/E1-CEPT framer. This framer is connected to one side on a PCM bus from one at 6.176/8.192MHz to four PCM bus at primary rate and on the other side to a line driver by a
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ANM035
29C96
29C96
192MHz
400ms.
1000H
106B
ANM035
TS16
mcr 106B
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0553-5006-IC
Abstract: HC49 67109510
Text: 29C310 MATRA MHS T1 CSU / ISDN PRI Transceiver Description The 29C310 is the first fully integrated transceiver for T1 CSU and ISDN Primary Rate Interface ISDN PRI applications at 1.544 MHz. This transceiver operates over 6,000 feet of 22 AWG twisted-pair cable without any
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29C310
29C310
29C3XX
29C300
29C301
29C304
0553-5006-IC
HC49
67109510
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DM 311 BG 40
Abstract: DM 311 BG 42 K/DM 311 BG 29 DM 311 BG 30
Text: Tem ic 29C94 MATRA MHS Multi-Channel HDLC Protocol Controller Description T he MHS 29C94 is a multi channel data link protocol controller device. It multiplexes/demultiplexes up to 32 full duplex data channels to support im plem entation of high speed data links based on
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29C94
29C94
29C3XX
29C96,
DM 311 BG 40
DM 311 BG 42
K/DM 311 BG 29
DM 311 BG 30
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tsr1-24
Abstract: mxt 211 RSR1-24 B18 IC marking code EL B17
Text: Tem ic 29C96 MATRA MHS T1-DS1/E1-CEPT Framer Formater Description T he 29C96 is a program m able CM OS device interfacing with T1 DS1 or E l (CEPT) transceivers. T he 29C96 supports following fram e form ats : • DS1 : 4 fram es (D M I), D4 (G704), ESF (G704),
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29C96
29C96
SLC-96
tsr1-24
mxt 211
RSR1-24
B18 IC marking code
EL B17
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Untitled
Abstract: No abstract text available
Text: Tem ic 29C318 MATRA MHS E l NIU / ISDN PRI Transceiver Description The 29C318 is the first fully integrated transceiver for El NIU and ISDN Primary Rate Interface ISDN PRI applications at 2.048 MHz. This transceiver operates over 2 km of 0.4 mm twisted-pair cable without any
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29C318
29C318
29C3XX
29C304A
29C305A
29C300
29C301
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mxt 211
Abstract: No abstract text available
Text: Tem ic 29C96 MATRA MHS T1-DS1/E1-CEPT Framer Formatter Description The 29C96 is a programmable CMOS device interfacing with T1-DS1 or El-CEPT transceivers. The 29C96 supports following frame formats : • DS1 : 4 frames DMI , D4 (G704), ESF (G704), SLC-96 (DMI), DDS (DMI)
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29C96
29C96
SLC-96
00470t.
mxt 211
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ITR30
Abstract: 0804H
Text: Tem ic 29C94 MATRA MHS Multi-Channel HDLC Protocol Controller Description The MHS 29C94 is a multi channel data link protocol controller device. It multiplexes/demultiplexes up to 32 full duplex data channels to support implementation of high speed data links based on
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29C94
MHS29C94
29C3XX
29C96,
29C94
ITR30
0804H
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Untitled
Abstract: No abstract text available
Text: Tem ic 29C95 MATRA MHS Multi-Channel ECMA 102/VI 10 Protocol Controller Description T he M HS 29C95 is a m ulti-channel data link protocol controlller device. It multiplexes/demultiplexes up to 32 full duplex data channels to support im plem entation of data links based on either the
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29C95
102/VI
29C95
29C3XX
29C96
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Untitled
Abstract: No abstract text available
Text: Temic MATRA MHS 29C95 Multi-Channel ECMA102/VHO Protocol Controller Description The MHS 29C95 is a multi-channel data link protocol controlller device. It multiplexes/demultiplexes up to 32 full duplex data channels to support implementation of data links based on either the
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29C95
ECMA102/VHO
29C95
102/V110
29C3XX
29C96
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Am29CPL100
Abstract: 29CPL151 am29cpl141 29CPL151-1 PL028 29CPI TLX2
Text: Prelim inary Advanced Micro Devices Am29CPL141 /Am29CPL151 CMOS Field Programmable Controller FPC DISTINCTIVE CHARACTERISTICS Up to 30-MHz clock rate Available in a wide selection of 28-pin packages, including SKINNYDIP • • Implements complex state machines
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Am29CPL141
/Am29CPL151
Am29PL141
64-word
32-bit
30-MHz
28-pin
WCP-12M-5/89-0
Am29CPL100
29CPL151
29CPL151-1
PL028
29CPI
TLX2
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