K8D3216UBC-pi07
Abstract: K5E5658HCM KAD070J00M KBH10PD00M K5D1257ACM-D090000 samsung ddr2 ram MTBF KBB05A500A K801716UBC k5d1g13acm k5a3281ctm
Text: Product Selection Guide Memory and Storage April 2005 MEMORY AND STORAGE SECTION A DRAM DDR2 SDRAM DDR SDRAM SDRAM RDRAM NETWORK DRAM MOBILE SDRAM GRAPHICS DDR SDRAM DRAM ORDERING INFORMATION FLASH NAND, OneNAND, NOR FLASH NAND FLASH ORDERING INFORMATION SRAM
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BR-05-ALL-002
K8D3216UBC-pi07
K5E5658HCM
KAD070J00M
KBH10PD00M
K5D1257ACM-D090000
samsung ddr2 ram MTBF
KBB05A500A
K801716UBC
k5d1g13acm
k5a3281ctm
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736-Pin
Abstract: LSI coreware library 64X144
Text: ADVANCE DATASHEET RC1800 Foundation Slice Family July 2005 The RapidChip RC1800 Foundation Platform ASIC Family, except for the RC1812 slice, is in NO-NEW-DESIGN Status as of July 2005. LSI Logic is not accepting new designs in this slice Family. Information in this datasheet is
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RC1800
RC1812
DB14-000253-04
DB14-000253-04,
DB14-000253-03
736-Pin
LSI coreware library
64X144
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MachXO sysIO Usage Guide
Abstract: LCMXO256C-4M100C LCMXO2280 lcmxo640c-3tn100i LCMXO640C-3FT256C LCMXO1200 LCMXO256 LCMXO2280E-4M132I LVCMOS15 LVCMOS25
Text: MachXO Family Data Sheet Version 02.3_4W February 2007 MachXO Family Data Sheet Introduction April 2006 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL
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TN1086)
TN1087)
TN1097)
MachXO sysIO Usage Guide
LCMXO256C-4M100C
LCMXO2280
lcmxo640c-3tn100i
LCMXO640C-3FT256C
LCMXO1200
LCMXO256
LCMXO2280E-4M132I
LVCMOS15
LVCMOS25
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DSC5002
Abstract: No abstract text available
Text: 256K x 36, 512K x 18 2.5V Synchronous ZBTTM SRAMs 2.5V I/O, Burst Counter Pipelined Outputs Features u 256K x 36, 512K x 18 memory configurations u Supports high performance system speed - 200 MHz Address and control signals are applied to the SRAM during one
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IDT71T65612/5812
IDT71T65612/5812
BG119
BQ165
x4033
DSC5002
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PDF
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723653
Abstract: 72V7290 72V3613 72V7250 72V3611 72V3623 72V72100 72V7230 72V7240 72V7260
Text: Selector Guide for FIFO Memory Products • Synchronous FIFOs SuperSync II, SuperSync™ SyncFIFO™, DualSync™ • Bi-Directional Synchronous FIFOs • Asynchronous FIFOs the leading provider of FIFO memories. July’00 IDT FIFO Memory Products Quick Reference Guide
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512-bit
16K-bit
64K-bit
128K-bit
256K-bit
512K-bit
100MHz
133MHz
723653
72V7290
72V3613
72V7250
72V3611
72V3623
72V72100
72V7230
72V7240
72V7260
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PDF
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ORT8850
Abstract: ORT8850H ORT8850L STM-64 STS-192
Text: Preliminary Product Brief May 2000 ORCA ORT8850 Field-Programmable System Chip Introduction Field-programmable system chips FPSCs bring a whole new dimension to programmable logic: FPGA logic and an embedded system solution on a single device. Lucent Technologies Microelectronics Group
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ORT8850
ORT8850
PN00-071FPGA
ORT8850H
ORT8850L
STM-64
STS-192
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LC4064ZE
Abstract: BSDL Files infineon LFXP6C-3FN256I "x-ray machine" K4H560838E LC4064 LC4256ZE LFXP10C-3F256I LFxP3C-3TN144C PCI x1 express PCB dimensions artwork
Text: LatticeXP Family Handbook HB1001 Version 03.4, September 2010 LatticeXP Family Handbook Table of Contents September 2010 Section I. LatticeXP Family Data Sheet Introduction Features . 1-1
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HB1001
TN1050
TN1049
TN1082
TN1074
LC4064ZE
BSDL Files infineon
LFXP6C-3FN256I
"x-ray machine"
K4H560838E
LC4064
LC4256ZE
LFXP10C-3F256I
LFxP3C-3TN144C
PCI x1 express PCB dimensions artwork
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PDF
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PU86
Abstract: No abstract text available
Text: QuickLogic PolarPro Device Data Sheet — 86-Pin TFBGA QL1P100 •••••• Combining Low Power, Performance, Density, and Embedded RAM • Quadrant-based segmentable clock networks Device Highlights 16 quad clock networks per device Low Power Programmable Logic
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86-Pin
QL1P100
PU86
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PDF
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Untitled
Abstract: No abstract text available
Text: QuickLogic PolarPro Data Sheet • • • • • • Combining Low Power, Performance, Density, and Embedded RAM Device Highlights 4 programmable global clock networks • Quadrant-based segmentable clock networks Low Power Programmable Logic 20 quad clock networks per device
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QL1P100
Abstract: No abstract text available
Text: QuickLogic PolarPro Device Data Sheet — QL1P075, QL1P100, QL1P200, and QL1P300 •••••• Combining Low Power, Performance, Density, and Embedded RAM • Quadrant-based segmentable clock networks Device Highlights 20 quad clock networks per device
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QL1P075,
QL1P100,
QL1P200,
QL1P300
QL1P100
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PDF
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AES1510
Abstract: aes2510 authentec ML67Q5250 ML67Q525 PB00X AuthenTec fingerprint XA06 XA04 XA05
Text: お客様各位 資料中の「沖電気」「OKI」等名称の OKI セミコンダクタ株式会社への変更について 2008 年 10 月 1 日を以って沖電気工業株式会社の半導体事業は OKI セミコン ダクタ株式会社に承継されました。 従いまして、本資料中には「沖電気工業株
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FJDL67Q5250-03
ML67Q5250
AES1510
128x8
AES2510
192x16
256x360pixels8bit/pixel500
AES1510
aes2510
authentec
ML67Q5250
ML67Q525
PB00X
AuthenTec fingerprint
XA06
XA04
XA05
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PDF
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723653
Abstract: BI 7284 72V7250 72V72100 72V7230 72V7240 72V7260 72V7270 72V7280 72V7290
Text: Selector Guide for FIFO Memory Products • Synchronous FIFOs SuperSync II, SuperSync™ SyncFIFO™, DualSync™ • Bi-Directional Synchronous FIFOs • Asynchronous FIFOs the leading provider of FIFO memories. Jan’00 IDT FIFO Memory Products Quick Reference Guide
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512-bit
16K-bit
64K-bit
128K-bit
512K-bit
7236x3/72V36x3
723653
BI 7284
72V7250
72V72100
72V7230
72V7240
72V7260
72V7270
72V7280
72V7290
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syscon
Abstract: LFEC1E-3T100C ips works 6CW3
Text: LatticeECP/EC Family Data Sheet Version 01.3 LatticeECP/EC Family Data Sheet Introduction November 2004 Preliminary Data Sheet Features − − − − − − • Extensive Density and Package Options • 1.5K to 41K LUT4s • 65 to 576 I/Os • Density migration supported
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36x36
18x18
DDR400
200MHz)
TN1052)
TN1057)
TN1053)
syscon
LFEC1E-3T100C
ips works
6CW3
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565 PLL
Abstract: linear application handbook national semiconductor pll 565 application CIII52001-1 EP3C10 EP3C120 EP3C16 EP3C25 EP3C40 EP3C55
Text: Section 1. Cyclone III Device Datasheet This section includes the following chapter: • Revision History Altera Corporation Chapter 1, Cyclone III Device Datasheet: DC and Switching Characteristics Refer to each chapter for its own specific revision history. For information on when each chapter was
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CIII52001-1
565 PLL
linear application handbook national semiconductor
pll 565 application
EP3C10
EP3C120
EP3C16
EP3C25
EP3C40
EP3C55
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Untitled
Abstract: No abstract text available
Text: Integrated Device Technology, Inc. CMOS Sync BiFlFO With Bus-Matching 256x36x2, 512x36x2, 1,024x36x2 PRELIMINARY IDT723624 IDT723634 IDT723644 NOTE: There is an errata notice on the last page and the corrections have not been incorporated into this document.
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256x36x2,
512x36x2,
024x36x2
IDT723624
IDT723634
IDT723644
2S771
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Untitled
Abstract: No abstract text available
Text: CMOS SyncBiFlFO 256x36x2, 512x36x2, 1024x36x2 IDT723622 IDT723632 IDT723642 Integrated D evice Technology, Inc. FEATURES: • Free-running CLKA and CLKB may be asynchronous or coincident simultaneous reading and writing of data on a single clock edge is permitted
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256x36x2,
512x36x2,
1024x36x2
IDT723622
IDT723632
IDT723642
IDT723622-256
IDT723632-512
IDT723642-1024
IDT723622/723632/723642
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Untitled
Abstract: No abstract text available
Text: In tegrated D e vice T e ch n o lo g y , Inc. CMOS Triple Bus SyncFIFOT With Bus-Matching 256x36x2, 512x36x2, 1024x36x2 PRELIMINARY IDT723626 IDT723636 IDT723646 NOTE: The errata notice on the last page describes corrections that have already been added to this document.
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OCR Scan
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256x36x2,
512x36x2,
1024x36x2
IDT723626
IDT723636
IDT723646
IDT723626-256
IDT723636-512
IDT723646-1024
36-bit
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PDF
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Untitled
Abstract: No abstract text available
Text: Integrated D eviœ Technology, lie . CMOS SyncBiFIFO with Bus-Matching 256x36x2, 512x36x2, 1,024x36x2 FEATURES: • Memory storage capacity: IDT723624—256 x 36 x 2 IDT723634-512 x 36 x 2 IDT723644-1,0 2 4 x 3 6 x 2 • Two independent clocked FIFOs buffering data in
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256x36x2,
512x36x2,
024x36x2
IDT723624
IDT723634
IDT723644
IDT723624--
IDT723634-512
IDT723644-1
36-bits
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Untitled
Abstract: No abstract text available
Text: 1dt Integrated Device Technology, Inc. 3.3 VOLT CMOS SyncBiFlFO WITH BUS-MATCHING 256x36x2, 512x36x2, 1,024 x 36 x 2 PRELIMINARY IDT72V3624 IDT72V3634 IDT72V3644 • Master Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings
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OCR Scan
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256x36x2,
512x36x2,
IDT72V3624
IDT72V3634
IDT72V3644
IDT72V3624-256
IDT72V3634-512
T72V3644-1
PK12B-1)
72V3624
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PDF
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Untitled
Abstract: No abstract text available
Text: IDT723622 IDT723632 IDT723642 CMOS SyncBiFIFO 256x36x2, 512x36x2, 1024x36x2 Integrated Device Technology, Inc. Advance inform ation for the IDT723622 Final for the IDT723632 Advance inform ation f o r the IDT723642 • • • • • • • Program mable Alm ost-Full and Alm ost-Em pty flags
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256x36x2,
512x36x2,
1024x36x2
IDT723622
IDT723632
IDT723642
T723642-1024
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PDF
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Untitled
Abstract: No abstract text available
Text: 3.3 VOLT CMOS SyncBiFlFO 256x36x2, 512x36x2, 1 ,02 4 x3 6 x 2 I dt PRELIMINARY IDT72V3622 IDT72V3632 IDT72V3642 Integrated Device Technology, Inc. FEATURES: • Memory storage capacity: IDT72V3622-256 x 36 x 2 1DT72V3632-512 x 36 x 2 IDT72V3642-1,024 x 36 X 2
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OCR Scan
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256x36x2,
512x36x2,
IDT72V3622
IDT72V3632
IDT72V3642
IDT72V3622-256
1DT72V3632-512
IDT72V3642-1
67MHz
PN120-1)
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PDF
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B17C
Abstract: No abstract text available
Text: _ INTEGRATED DEVICE. IDT •b6E D 4025771 DGlBlb'i 4flT ADVANCED INFORMATION CMOS SyncBiFlFO IDT723622 256x36x2,1024x36x2 IDT723642 Integrated Device Technology, Inc. FEATURES: • Free-running CLKA and CLKB may be asynchronous or coincident • Two independent clocked FIFOs buffering data in oppo
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IDT723622
256x36x2
1024x36x2
IDT723642
IDT723622â
IDT723642â
67MHz
Z1A21
IDT723622/42
4A25771
B17C
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PDF
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bd-9b
Abstract: No abstract text available
Text: MOSEL- VITELIC MS76542 256x36x2 BIDIRECTIONAL FIFO Features Description • ■ ■ ■ ■ The MS76542 contains two FIFO buffers which operate in parallel but opposite directions for bidirectional data buffering. The two FIFO buffers are each organized as 256 words by 36 bits. The
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MS76542
256x36x2
MS76542-25QC
MS76542-30QC
MS76542-35QC
MS76542
bd-9b
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fifo asi cypress
Abstract: No abstract text available
Text: CY7C43624 CY7C43634/CY7C43644 CY7C43664/CY7C43684 PRELIMINARY CYPRESS 256/512/1K/4K/16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching Fully asynchronous and sim ultaneous read and write operation permitted Mailbox bypass register for each FIFO Parallel and Serial Programmable Almost-Full and
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CY7C43624
CY7C43634/CY7C43644
CY7C43664/CY7C43684
256/512/1K/4K/16K
128-pin
IDT723624/34/44
256x36x2
CY7C43624)
fifo asi cypress
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