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    UNITRODE

    Abstract: No abstract text available
    Text: bq4014/bq4014Y 256Kx8 Nonvolatile SRAM Features ➤ Data retention in the absence of power ➤ Automatic write-protection during power-up/power-down cycles ➤ Industry-standard 32-pin 256K x 8 pinout ➤ Conventional SRAM operation; unlimited write cycles


    Original     		PDF bq4014/bq4014Y 32-pin 10-year 256Kx8 bq4014 152-bit UNITRODE

    K6F2008S2E

    Abstract: K6F2008S2E-F
    Text: K6F2008S2E Family CMOS SRAM Document Title 256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History Draft Date Remark Preliminary 0.0 Initial Draft February 28, 2001 1.0 Finalize September 27, 2001 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and


    Original     		PDF K6F2008S2E 256Kx8 K6F2008S2E-F

    IBM0418A41NLAB

    Abstract: IBM0418A81NLAB IBM0436A41NLAB IBM0436A81NLAB
    Text: IBM0436A41NLAB IBM0418A41NLAB IBM0418A81NLAB IBM0436A81NLAB 8Mb 256Kx36 & 512Kx18 and 4Mb (128Kx36 & 256Kx18) SRAM . Features • 8Mb: 256K x 36 or 512K x 18 organizations 4Mb: 128K x 36 or 256K x 18 organizations • Registered outputs • 30 Ω drivers


    Original     		PDF IBM0436A41NLAB IBM0418A41NLAB IBM0418A81NLAB IBM0436A81NLAB 256Kx36 512Kx18) 128Kx36 256Kx18) crrL3325 IBM0418A41NLAB IBM0436A81NLAB

    K7A401800B-QC

    Abstract: K7A401809B K7A401809B-QC K7A403200B-QC K7A403209B K7A403209B-QC K7A403609B K7B401825B-QC K7B403225B-QC
    Text: K7A403609B K7A403209B K7A401809B 128Kx36/x32 & 256Kx18 Synchronous SRAM Document Title 128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM Revision History History Draft Date Remark 0.0 1. Initial draft May. 15. 2001 Preliminary 0.1 1. Changed DC parameters


    Original     		PDF K7A403609B K7A403209B K7A401809B 128Kx36/x32 256Kx18 128Kx36 128Kx32 256Kx18-Bit 570mA 490mA K7A401800B-QC K7A401809B K7A401809B-QC K7A403200B-QC K7A403209B K7A403209B-QC K7A403609B K7B401825B-QC K7B403225B-QC

    K6X4016C3F

    Abstract: K6X4016C3F-B K6X4016C3F-F K6X4016C3F-Q
    Text: CMOS SRAM K6X4016C3F Family Document Title 256Kx16 bit Low Power full CMOS Static RAM Revision History Revision No. History Draft Date Remark 0.0 Initial draft July 26, 2002 Preliminary 0.1 Revised Added Commercial Product. Deleted 44-TSOP2-400R Package Type.


    Original     		PDF K6X4016C3F 256Kx16 44-TSOP2-400R K6X4016C3F-B K6X4016C3F-F K6X4016C3F-Q

    K7A401800B

    Abstract: K7A401800B-QC K7A401809B-QC K7A403200B K7A403200B-QC K7A403209B-QC K7A403600B K7B401825B-QC K7B403225B-QC
    Text: K7A403600B K7A403200B K7A401800B 128Kx36/x32 & 256Kx18 Synchronous SRAM Document Title 128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM Revision History History Draft Date Remark 0.0 1. Initial draft May. 15. 2001 Preliminary 0.1 1. Changed DC parameters


    Original     		PDF K7A403600B K7A403200B K7A401800B 128Kx36/x32 256Kx18 128Kx36 128Kx32 256Kx18-Bit 350mA 290mA K7A401800B K7A401800B-QC K7A401809B-QC K7A403200B K7A403200B-QC K7A403209B-QC K7A403600B K7B401825B-QC K7B403225B-QC

    IBM0418A8ACLAB

    Abstract: IBM0436A4ACLAB IBM0436A8ACLAB IBM0418A4ACLAB
    Text: . IBM0418A4ACLAB IBM0436A8ACLAB Preliminary IBM0418A8ACLAB IBM0436A4ACLAB 8Mb 256Kx36 & 512Kx18 and 4Mb (128Kx36 & 256Kx18) SRAM Features • 8Mb: 256K x 36 or 512K x 18 organizations 4Mb: 128K x 36 or 256K x 18 organizations • 0.25 Micron CMOS technology


    Original     		PDF IBM0418A4ACLAB IBM0436A8ACLAB IBM0418A8ACLAB IBM0436A4ACLAB 256Kx36 512Kx18) 128Kx36 256Kx18) crlh3320 IBM0418A8ACLAB IBM0436A4ACLAB IBM0436A8ACLAB IBM0418A4ACLAB

    K6R1004C1D

    Abstract: No abstract text available
    Text: PRELIMINARY Preliminary PRELIMINARY K6R1004C1D CMOS SRAM Document Title 256Kx4 Bit with OE High-Speed CMOS Static RAM(5.0V Operating). Revision History Rev. No. History Rev. 0.0 Rev. 0.1 Rev. 0.2 Initial release with Preliminary. Current modify 1. Delete 15ns speed bin.


    Original     		PDF K6R1004C1D 256Kx4 32-SOJ-400 K6R1004C1D

    K7D803671B-HC33

    Abstract: K7D803671B-HC30 K7D801871B-HC35 K7D801871B-HC37 K7D803671B K7D803671B-HC25 K7D803671B-HC35 K7D803671B-HC37
    Text: K7D803671B K7D801871B 256Kx36 & 512Kx18 SRAM Document Title 8M DDR SYNCHRONOUS SRAM Revision History Rev No. History Draft Data Remark Rev. 0.0 -Initial document. July. 2000 Advance Rev. 0.1 -ZQ tolerance changed from 10% to 15% Aug. 2000 Advance Rev. 0.2


    Original     		PDF K7D803671B K7D801871B 256Kx36 512Kx18 -HC16 012MAX K7D803671B-HC33 K7D803671B-HC30 K7D801871B-HC35 K7D801871B-HC37 K7D803671B K7D803671B-HC25 K7D803671B-HC35 K7D803671B-HC37

    K7N401801B

    Abstract: K7N403601B
    Text: K7N403601B K7N401801B 128Kx36 & 256Kx18 Pipelined NtRAMTM Document Title 128Kx36 & 256Kx18-Bit Pipelined NtRAMTM Revision History History Draft Date Remark 0.0 1. Initial document. May. 15. 2001 Preliminary 0.1 1. Changed DC parameters Icc ; from 350mA to 290mA at -16,


    Original     		PDF K7N403601B K7N401801B 128Kx36 256Kx18 256Kx18-Bit 350mA 290mA 330mA 270mA K7N401801B K7N403601B

    K7B801825B

    Abstract: K7B803625B
    Text: K7B803625B K7B801825B 256Kx36 & 512Kx18 Synchronous SRAM Document Title 256Kx36 & 512Kx18-Bit Synchronous Burst SRAM Revision History Rev. No. History Draft Date Remark 0.0 Initial draft May. 18 . 2001 Preliminary 0.1 Add x32 org part and industrial temperature part


    Original     		PDF K7B803625B K7B801825B 256Kx36 512Kx18 512Kx18-Bit 119BGA 225MHz K7B801825B K7B803625B

    CY7C197

    Abstract: No abstract text available
    Text: CY7C197 256Kx1 Static RAM Features vided by an active LOW chip enable CE and three-state drivers. The CY7C197 has an automatic power-down feature, reducing the power consumption by 75% when deselected. • High speed — 12 ns Writing to the device is accomplished when the chip enable


    Original     		PDF CY7C197 256Kx1 CY7C197

    K6F4016U6G-EF70

    Abstract: K6F4016U6G K6F4016U6G-F K6F4016U6GE
    Text: Preliminary CMOS SRAM K6F4016U6G Family Document Title 256Kx16 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History 0.0 Initial Draft Draft Date Remark June 11, 2003 Preliminary The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and


    Original     		PDF K6F4016U6G 256Kx16 55/Typ. 35/Typ. K6F4016U6G-EF70 K6F4016U6G-F K6F4016U6GE

    IBM0418A4ANLAB

    Abstract: IBM0418A8ANLAB IBM0436A4ANLAB IBM0436A8ANLAB
    Text: . Preliminary IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb 256Kx36 & 512Kx18 and 4Mb (128Kx36 & 256Kx18) SRAM Features • 8Mb: 256K x 36 or 512K x 18 organizations 4Mb: 128K x 36 or 256K x 18 organizations • 0.25µ CMOS technology • Synchronous Register-Latch Mode of Operation


    Original     		PDF IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 256Kx36 512Kx18) 128Kx36 256Kx18) crlL3325 IBM0418A8ANLAB IBM0436A4ANLAB

    Untitled

    Abstract: No abstract text available
    Text: bq4014/bq4014Y 256Kx8 Nonvolatile SRAM Features General Description ➤ Data retention in the absence of power The CMOS bq4014 is a nonvolatile 2,097,152-bit static RAM organized as 262,144 words by 8 bits. The integral control circuitry and lithium energy


    Original     		PDF bq4014/bq4014Y 256Kx8 bq4014 152-bit 32-pin 10-year

    bq4014

    Abstract: BQ4014MB-120 BQ4014MB-85 bq4014Y BQ4014YMB-85
    Text: bq4014/bq4014Y 256Kx8 Nonvolatile SRAM Features General Description ➤ Data retention in the absence of power The CMOS bq4014 is a nonvolatile 2,097,152-bit static RAM organized as 262,144 words by 8 bits. The integral control circuitry and lithium energy


    Original     		PDF bq4014/bq4014Y 256Kx8 bq4014 152-bit 32-pin 10-year BQ4014MB-120 BQ4014MB-85 bq4014Y BQ4014YMB-85

    Untitled

    Abstract: No abstract text available
    Text: OJ bq4014/bq4014Y UNITRODE- 256Kx8 Nonvolatile SRAM Features > Data retention in the absence of power > Automatic write-protection dur­ ing power-up/power-down cycles >• Industry-standard 32-pin 256K x 8 pinout >• Conventional SEAM operation; unlimited write cycles


    OCR Scan     		PDF bq4014/bq4014Y 256Kx8 bq4014 152-bit 256Kx

    LC3516AL-10

    Abstract: LC3516A-10
    Text: SANYO SEMICONDUCTOR - 3 B E C ORP D • 7 q ^ 7 Q 7b □□ 054 53 1 H9 CMOS DYNAMIC RAM Capacity Access Tim e Organization Words X Bits 1MX1 1M 256KX4 Type N o . T rac ns max L C 3 2 1 0 0 0 -1 0 /1 2 L C 3 2 1 0 0 0 J -1 0 /1 2 L C 3 2 10O O Z-1 0 /1 2


    OCR Scan     		PDF SOJ26 S0J26 256KX4 LC3516A-10 LC3516A-12 LC3516AL-10 LC3516AL-12 LC3516AM-10 LC3516AM-12 MFP24

    schematic diagram cga to vga

    Abstract: DD11D1D SCHEMATIC mda VGA board cga ega vga RAMDAC DIP BT477 TTL sync video CGA to vga schematic diagram cga to vga circuit convert ega to vga I334 cga to vga
    Text: UM•■ ■■• ■■ ■■ai i v a n i r à 82C453 Ultra VGA Graphics Controller ■ High Performance VRAM VGA optimized for 800x600 and 1024x768, 16 and 256 color, display resolutions interlaced/non-interlaced ■ 4 VRAMs (256Kx4) support all Super VGA


    OCR Scan     		PDF 82C453 800x600 1024x768, 256Kx4) 1024x768 160-Pin G011GHD schematic diagram cga to vga DD11D1D SCHEMATIC mda VGA board cga ega vga RAMDAC DIP BT477 TTL sync video CGA to vga schematic diagram cga to vga circuit convert ega to vga I334 cga to vga

    DDC Panel

    Abstract: CYBER9320 Trident vga ibm crt monitor circuit diagram Non VGA Video Controller IC flat crt circuit diagram PQ-32/plasma 640x480
    Text: / Trident CYBER9320 Flat Panel Controller Features Highly Integrated Design • Requires only one 256Kxl6 DRAM for 1024x768-16 color SVGA solution • Built-in LUT-DAC composed of 256x18 color look-up table • Dual loop memory and video clock • Two-chip solution 9320 and 256Kxl6 for 512K


    OCR Scan     		PDF CYBER9320TM 256Kxl6 1024x768-16 256x18 256Kxl6) 208-pin 1024x768-16, 800x600-256, 640x480-64K, 640x480-256 DDC Panel CYBER9320 Trident vga ibm crt monitor circuit diagram Non VGA Video Controller IC flat crt circuit diagram PQ-32/plasma 640x480

    Untitled

    Abstract: No abstract text available
    Text: ¡ n t I» P ftE U R fl 11 " H ì1 51C256H HIGH PERFORMANCE RIPPLEMODE 256Kx 1 CHMOS DYNAMIC RAM 51C256H-10t 51C256H-12 51C256H-15 51C256H-20 100 120 150 200 Maximum Column Address Accsss Tims (ns 40 50 65 85 Ripplemode Cycle Tims (ns) 50 60 75 95 Maximum Access Tims (ns)


    OCR Scan     		PDF 51C256H 256Kx 51C256H-10t 51C256H-12 51C256H-15 51C256H-20 tRcB170 51C256H 144x1

    HY514264

    Abstract: No abstract text available
    Text: •HYUNDAI HY514264B 256Kx16, Extended Data Out mode DESCRIPTION This family is a 4M bit dynamic RAM organized 262,144 x 16-bit configuration with CMOS DRAMs. The circuit and process design allow this device to achieve high performance and low power dissipation. Optional features are access time 50, 60


    OCR Scan     		PDF HY514264B 256Kx16, 16-bit 40-pin 400mil) 16-bits 256Kx16 HY514264

    Untitled

    Abstract: No abstract text available
    Text: i 128K X 36, 256KX 18, 3.3V SYNCHRONOUS SRAMS WITH ZBT FEATURE, BURST COUNTER AND FLOW-THROUGH OUTPUTS :$*&&* 4« *»»« tK fc « * 'S * * * * ; 4ÎK«« '* * * « ^ iL j; PRELIMINARY IDT71 V2557,IDT71 V2559 IDT71V3557, IDT71V3559 FEATURES: The IDT71 Vx557/59 contain address, data-in and control signal regis­


    OCR Scan     		PDF 256KX IDT71 V2557 V2559 IDT71V3557, IDT71V3559 Vx557/59

    256Kx4 SRAM

    Abstract: EDI8M4257C
    Text: mD\ EDI8M4257C Electronic Designs Inc. High Speed Megabit SRAM Module 256Kx4 SRAM CMOS, High Speed Module Features The EDI8M4257C is a Megabit 256Kx4-bit High Speed Static RAM Module with four bi-directional input/ output lines. The module is constructed of four 256Kx1


    OCR Scan     		PDF EDI8M4257C 256Kx4 EDI8M4257C 256Kx4-bit) 256Kx1 181256C 256Kx4 SRAM