2-BIT DOWN COUNTER Search Results

SN54HC

Abstract: TEXAS CT 306 IC U114
Contextual Info: SN54HC190, SN54HC191, SN74HC190, SN74HC191 SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS 2 6 8 4 . DECEMBER 1 9 3 2 - Single Down/Up Count Control Line •

Contextual Info: MULTIFUNCTION TIMER MFT ST9+/ MULTI-FUNCTIONS TIMER / 1 MFT Main Features 2 Input and 2 Output pins independently configurable 16-bit counter and 8-bit prescaler Up or down counter, external or internal clock 2 Capture/Reload Registers (16-bit) 2 Compare Registers (16-bit)

TC40102BP

Contextual Info: i;æ§ND^oLLKfcGRATEDC|RCUT TC40102BP, TC40103BP TC4C102BP 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNfER 2-Decade BCD Type TC40103BP 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTER (8-Bit Bynary Type) The TC40102BP and TC40103BP are 8-stage presettable synchronous down counters.

LS192

Abstract: master slave jk flip flop LS193
Contextual Info: T54tSt&2/193 T74ütt92/193 LS192 - PRESETTABLE BCD/DECADE UP/DOWN COUNTER LS193 - PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER DESCRIPTION The T54LS192/T74LS192 is a UP/DOWN BCD De­ cade 8421 Counter and the T54LS193/T74LS193 is an UP/DOWN Modulo-16 Binary Counter. Sepa­

IC 74LS192

Abstract: ic 74193 74193 state diagram 74193 pin configuration ic 74192 pin configuration 74192 ic pin diagram of counter ic 74193 ic 74192 74192 of ic 74ls193
Contextual Info: 7 4 1 9 2 , 7 4 1 9 3 , LS192, LS193 Signelics Counters '192 Presettable BCD Decade Up/Down Counter '193 Presettable 4-Bit Binary Up/Down Counter Product Specification Logic Products FEATURES TYPE • Synchronous reversible 4-bit binary counting TYPICAL fMAx

74 LS 193 n

Contextual Info: T54tSt&2/193 T74ütt92/193 LS192 - PRESETTABLE BCD/DECADE UP/DOWN COUNTER LS193 - PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER DESCRIPTION The T54LS192/T74LS192 is a UP/DOWN BCD De­ cade 8421 Counter and the T54LS193/T74LS193 is an UP/DOWN Modulo-16 Binary Counter. Sepa­

SMD 4E

Abstract: smd .8k cd motor cd rom motor C868-1SG C515-L C508-4E 10-BIT P-MQFP-80
Contextual Info: Timers/ Counters 16-Bit Interrupts vectors/ Levels Serial I/O FCAN 2.0B active PWM Mul./Div. Unit Data Pointers (16-Bit) Hardware Power Down Wakeable Power Down Mode 512 32 8/10Bit 4 12 / 2 USART - 7-ch - 1 - ! P-MQFP-44 CCU for DC motor control, Interrupt

Truth Table 74192

Abstract: pin diagram of counter ic 74193 74193 truth table ic 74192 74192 ic Truth Table 74193 of IC 74193 TC40192BPJC40193BP IC TTL 74193 TC40192BP/TC40193BP
Contextual Info: TC40192BPJC40193BP C2M 0 S DIGITAL INTEGRATED CIRCUIT SILICO N MONOLITHIC TC40192BP PRESETTABLE BCD UP/DOWN COUNTER Dual Clock with Reset TC40193BP PRESETTABLE BINARY UP/DOWN COUNTER (Dual Clock with Reset) T C 4 0 1 9 2 B P / T C40193BP i synchronous 4-bit up/down

TC40102BP

Abstract: TC40103BP S-10 TC4071BP
Contextual Info: TC40102BP, TC40103BP ^ S ïïT 11“CIRCUIT T C40102BP 8-STAGE PRESETTABLE SYNCHkOUOUS DOWN COUNTER 2-Decade BCD Type T C40103BP 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTER (8-Bit Bynary Type) The TC40102BP and TC40103BP are 8-stage presettable synchronous down counters. Output terminal CO/ZD is

Contextual Info: SN54HC190, SM54HC191, SN74HC190, SN74HC191 SYNCHRONOUS 4 BIT UP/DOWN DECADE AND BINARY COUNTERS D 2 6 8 4 , DECEMBER 1 9 8 2 - Single Down/Up Count Control Line • Look-Ahead Circuitry Enhances Speed of Cascaded Counters • Fully Synchronous in Count Modes

8 bit multiplier using vhdl code

Abstract: ado1 "Single-Port RAM"
Contextual Info: Designing ispLSI 6000 Devices in the Synplicity Environment ® 2. c4r4pl: four counters up/down, 8/16 bits, parallel load are configured as a 16-bit counter, default is up. Counter sizes can be independently changed to 8 or 16 bits for each bank; default is 16-bit. Once up, down

vhdl code for parallel to serial shift register

Abstract: isplsi architecture
Contextual Info: Designing ispLSI 6000 Devices in the Synplicity Environment ® 2. c4r4pl: four counters up/down, 8/16 bits, parallel load are configured as a 16-bit counter, default is up. Counter sizes can be independently changed to 8 or 16 bits for each bank; default is 16-bit. Once up, down

VG264265

Abstract: VG264260B
Contextual Info: VG264260BJ 262,144x16-Bit CMOS Dynamic RAM VIS TRUTH TABLE 2-CKE Notes: 1-4 CKEn-1 CKE n CURRENT STATE COMANDn ACTIONn L L Power-Down X Maintain Power-Down Self Refresh X Maintain Self Refresh Power-Down COMMAND INHIBIT or NOP Exit Power-Down 5 Self Refresh

TC40102BP

Abstract: TC40102 Digital Pulse Counter Two Digit TC40103BP S-10 TC4071BP
Contextual Info: TC40102BP, TC40103BP C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC T C40102BP 8-STAGE PRESETTABLE SYNCHkOUOUS DOWN COUNTER 2-Decade BCD Type T C40103BP 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTER (8-Bit Bynary Type) The TC40102BP and TC40103BP are 8-stage presettable

ZD 282

Abstract: TC40102BP
Contextual Info: TC40102BP, TC40103BP C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC40102BP 8-STAGE PRESETTABLE SYNCHS;0i»0Ui DOwN COUNTER 2-Decade BCD Type TC4Q1Q3BP 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTER (8-Bit Bynary Type) The TC40102BP and TC40103BP are 8-stage presettable

MSI IC

Abstract: Signetics 565 HEF4526BP programmable counter ic HEF SCHMITT-TRIGGER IN HEF4526BT GQS210S HEF4526B HEF4526BD hef4526
Contextual Info: NAPC/ SIGNETICS 2TE D • ^53^24 I I I0 5 2 1 0 0 L 5 M HEF4526B MSI T-VS-23-21 PROGRAMMABLE 4-BIT BINARY DOWN COUNTER The HEF4526B is a synchronous programmable 4-bit binary down counter with an active HIGH and an active LOW clock input CPq, CPi , an asynchronous parallel load input (PL), four parallel inputs (Pg

Contextual Info: Rev 0; 7/07 I2C, 32-Bit, Binary Counter Clock with 64-Bit ID Features The DS1372 is a 32-bit binary up counter and 24-bit down counter with a unique 64-bit ID. The counters, ID, configuration, and status registers are accessed using an I 2 C serial interface. The DS1372 includes a

DS1372

Abstract: 32 Bit Counter San Ace 40 24v
Contextual Info: Rev 0; 7/07 I2C, 32-Bit, Binary Counter Clock with 64-Bit ID Features The DS1372 is a 32-bit binary up counter and 24-bit down counter with a unique 64-bit ID. The counters, ID, configuration, and status registers are accessed using an I 2 C serial interface. The DS1372 includes a

Contextual Info: SAMSUNG SEMICONDUCTOR INC KS54HCTLS - j Q j KS74HCTLS D2 TËJ 7^4142 ODGb42ñ 2 Synchronous 4-Bit Up/Down Binary Counters T ^ r - ^ 3 -0 7 FEATURES DESCRIPTION • Single down/up count control line • Look-ahead circuitry enhances speed of cascaded counters

gd4029b

Abstract: ic CMOS 4029B GD402 40298 goldstar scheme
Contextual Info: GOLDSTAR TECHNOLOGY INC-, D4E D | 4 0 2 0 7 5 7 OOOlbL.2 3 | ~ f T -*/£ -2 3 ‘ O l . 4 0 2 8 7 5 7 G O LD STA R TECHNO LO GY IN C . 04E 01662 D GD4029B SYNCHRONOUS UP/DOWN COUNTER DESCRIPTIO N — The 4029B is a Synchronous Edge-Triggered Up/Down 4-Bit Binary/BCD Decade

AM9513 counter

Abstract: amd 9513 Celeritous Technical Services AM9513 Patriot Scientific CTS9513-2 am 9513 timer CTSC9513A DIP-40 PLCC-44
Contextual Info: Celeritous Technical Services Corp 3308 34th St Lubbock, Texas 79410 800.687.6510 / 806.793.0708 FAX 806.793.0710 http://www.celeritous.com CTS9513-2 5 Chan 16 bit 20MHz Counter/Timer FUNCTIONS • • • • • • • • Five 16 bit programmable up/down counters

8 bit binary to 7 segment

Abstract: 4 DIGIT DECADE COUNTER 4 digit 7 segment decoder 6-DIGIT DECADE COUNTER 4 bcd digit counter TC5054 TC5032 TC5051 HIGH FREQUENCY DECADE COUNTER BCD counter
Contextual Info: X41 Type Number TC40103B TC40107B TC40117B TC40161B TC40163B TC40174B TC40175B TC40192B TC40193B TC4502B Function 8-STAGE PRESETTABLE DOWN COUNTER 8-BIT BINARY TYPE DUAL 2-INPUT NAND BUFFER/DRIVER PROGRAMMABLE DUAL 4-BIT TERMINATOR PROGRAMMABLE BINARY COUNTER WITH ASYNCHRONOUS CLEAR

TTL 74192

Abstract: 74193 counter ttl 74193 pin diagram of 74192 74192 counter 74193 state diagram 74193 state diagram up counter 74193 74192 74193 A
Contextual Info: TTL/MSI 9360/54192, 74192 9366/54193, 74193 UP/DOWN DECADE AND BINARY COUNTERS DESCRIPTIO N - The T T L /M S I 9360/5 4 1 9 2 , 74192 is a synchronous Up/Down BCD Decade Cbunter, and the T T L /M S I 9366/5 4 1 9 3 , 74193 is a synchronous Up/Down 4-Bit Binary Counter. Both counters have separate up/down clocks, parallel load facility, terminal

Contextual Info: July 1989 Semiconductor & DM54LS491A/DM74LS491A 10-Bit Counter General Description Features The ten-bit counter can count up, count down, set, and load 2 LSB’s, 2 MSB’s and 6 middle bits high or low as a group. All operations are synchronous with the clock. SET over­