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    2 IN PUT TTL XOR GATES Search Results

    2 IN PUT TTL XOR GATES Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TLP5702H Toshiba Electronic Devices & Storage Corporation Photocoupler (Gate Driver Coupler), High-Topr / IGBT driver, 5000 Vrms, SO6L Visit Toshiba Electronic Devices & Storage Corporation
    TLP5705H Toshiba Electronic Devices & Storage Corporation Photocoupler (Gate Driver Coupler), High-Topr / IGBT driver, 5000 Vrms, SO6L Visit Toshiba Electronic Devices & Storage Corporation
    TB67H481FTG Toshiba Electronic Devices & Storage Corporation Stepping and Brushed Motor Driver /Bipolar Type / Vout(V)=50 / Iout(A)=3.0 / IN input type / VQFN32 Visit Toshiba Electronic Devices & Storage Corporation
    GT30J110SRA Toshiba Electronic Devices & Storage Corporation IGBT, 1100 V, 60 A, Built-in Diodes, TO-3P(N) Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T125FK Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, SOT-765 (US8), -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation

    2 IN PUT TTL XOR GATES Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    B272

    Abstract: 149-IO
    Text: ispLSI 3192 High Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.


    Original     		Faste14 3192-100LM 240-Pin 3192-100LB272 272-Ball 3192-70LM 3192-70LB272 3192-70LMI B272 149-IO PDF

    B272

    Abstract: z 0607
    Text: ispLSI 3192 Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic


    Original     		3192-100LQ 240-Pin 3192-100LB272 272-Ball 3192-70LQ 3192-70LB272 3192-70LQI B272 z 0607 PDF

    Untitled

    Abstract: No abstract text available
    Text: Specifications ispLSI 3192 ispLSI 3192 High Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    Original     		PDF

    B272

    Abstract: No abstract text available
    Text: ispLSI 3192 High Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.


    Original     		Faste14 3192-100LM 240-Pin 3192-100LB272 272-Ball 3192-70LM 3192-70LB272 3192-70LMI B272 PDF

    3192-70LQI

    Abstract: B272
    Text: ispLSI 3192 High Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.


    Original     		Faste14 3192-100LQ 240-Pin 3192-100LB272 272-Ball 3192-70LQ 3192-70LB272 3192-70LQI 3192-70LQI B272 PDF

    Untitled

    Abstract: No abstract text available
    Text: ispLSI 3192 High Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.


    Original     		3192-100LM 3192-100LB272 3192-70LM 3192-70LB272 240-Pin 272-Ball 3192-70LMI PDF

    af201

    Abstract: F2018 AM211 am 332 F2017 SEM 2005 16 PINS inverter
    Text: Am3550 Mixeçt ÉCL/TTL I/O Mask-Programmable Gate Array PRELIMINARY DISTINCTIVE CHARACTERISTICS Up to 5228 equivalent gates - 576 internal cells - Up to 124 l/O s H igh-perform ance, low -pow er ECL internal gates - W orst case Tpd = 0.6 ns Hi-Speed = 0.7 ns (Medium)


    OCR Scan     		Am3550 7321A 7322A af201 F2018 AM211 am 332 F2017 SEM 2005 16 PINS inverter PDF

    Untitled

    Abstract: No abstract text available
    Text: Lattice' ispLSr and pLSI' 2032 ; ; ; Semiconductor •■■Corporation High Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — — — — — 1000 PLD Gates 32 I/O Pins, Two Dedicated Inputs 32 Registers


    OCR Scan     		2032-135LJ 2032-135LT 2032-135LT44 2032-110LJ 2032-110LT 2032-110LT44 2032-80LJ 2032-80LT 2032-80LT44 2032-150LJ PDF

    af201

    Abstract: AOX2051 Am319 AF211 AF212 AF203 AF216 AM2024 ls 11s AM211
    Text: y i Am3550 MixeqT ECL/TTL I/O Mask-Programmable Gate Array • — PRELIMINARY DISTINCTIVE CHARACTERISTICS Up to 5228 equivalent gates - 576 internal cells - Up to 124 l/O s H igh-perform ance, low -pow er ECL internal gates - W orst case Tpd = 0.6 ns Hi-Speed


    OCR Scan     		Am3550 Am3550 wf010980 wfr02682 7321A 07322a af201 AOX2051 Am319 AF211 AF212 AF203 AF216 AM2024 ls 11s AM211 PDF

    TR20X3

    Abstract: DFI01 OR02D
    Text: December 1989 FGA S eries A S PE C T- ECL G ate A rrays General Description The FGA Series is a new generation of ECL gate arrays based on National’s ASPECT process. These advanced ECL gate arrays, ranging from 200 to over 30,000 equiva­ lent gates, offer typical internal propagation delays of


    OCR Scan     		PDF

    ispls11024

    Abstract: No abstract text available
    Text: Lattice ispLSI 1024 ; ; ; Semiconductor • ■ ■ Corporation High Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 4000 PLD Gates — 48 I/O Pins, Six Dedicated Inputs


    OCR Scan     		Military/883 20PTXOR 16-Bit ispls11024 PDF

    Untitled

    Abstract: No abstract text available
    Text: Latticc ispLSI 3256 ; ; ; Semiconductor •■■ Corporation High Density Programmable Logic Functional Block Diagram Features HIGH-DENSITY PROGRAMMABLE LOGIC — 1281/0 Pins — 11000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    OCR Scan     		160-M 0212Aisp/3256 3256-70LM 160-Pin 3256-50LM PDF

    Untitled

    Abstract: No abstract text available
    Text: Lattice ispLSr 1016 H I Semiconductor •■■ Corporation In-System Programmable High Density PLD Functional Block Diagram Features • HIGH-DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs


    OCR Scan     		Military/883 44-Pin 1016-80LT44 1016-60LJ 1016-60LT44 1016-60LJI PDF

    Untitled

    Abstract: No abstract text available
    Text: Q V Lattica V Ï Î i f c ispLSI3256A !Semiconductor I Corporation High Density Programmable Logic F u n c tio n a l B lo c k D iagram F eatures • HIGH-DENSITY PROGRAMMABLE LOGIC — 128 I/O Pins — 11000 PLD Gates — 384 Registers — High Speed Global Interconnect


    OCR Scan     		0212/3256A 256A-90LM* 256A-90LQ 256A-70LM* 256A-70LQ 256A-50LM* 160-Pin PDF

    Untitled

    Abstract: No abstract text available
    Text: f C-S u Lattice ispLSI3448 !Semiconductor •Corporation Features High-Density Programmable Logic Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 224 I/O — 20000 PLD Gates — 672 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    OCR Scan     		3448-90LB432 3448-70LB432 432-Ball PDF

    Untitled

    Abstract: No abstract text available
    Text: Lattica ispLSI 3256 ;Semiconductor I Corporation High Density Programmable Logic Functional Block Diagram Features HIGH-DENSITY PROGRAMMABLE LOGIC — 128 1/0 Pins — 11000 PLD Gates — 384 Registers — High Speed Global Interconnect — W ide Input Gating for Fast Counters, State


    OCR Scan     		160-MQFP/3256 3256-70LM 160-Pin 3256-50LM 041A-08isp/3256 PDF

    Untitled

    Abstract: No abstract text available
    Text: Lattice ispLSI and pLSF 2032 I Semiconductor I Corporation High Density Programmable Logic Functional Block Diagram Features • HIGH DENSITY PROGRAMMABLE LOGIC — — — — — 1000 PLD Gates 32 I/O Pins, Two Dedicated Inputs 32 Registers High Speed Global Interconnect


    OCR Scan     		44-Pin 48-Pin PDF

    Untitled

    Abstract: No abstract text available
    Text: Lattice' ispLSI 3256A | Semiconductor I Corporation In-System Programmable High Density PLD Functional Block Diagram Features HIGH-DENSITY PROGRAMMABLE LOGIC — 1281/0 Pins — 11000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    OCR Scan     		256A-90LM* 160-Pin 256A-90LQ 256A-70LM* ispLSI3256A-70LQ 256A-50LM* PDF

    Untitled

    Abstract: No abstract text available
    Text: Lattice is p L S _ _ _ _ Semiconductor • ■ ■ ■ Corporation r a n d p L S Im 1 0 1 6 E High-Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — — — — — 2000 PLD Gates 32 I/O Pins, Four Dedicated Inputs


    OCR Scan     		iSp1C16 1016E 1016E-125LJ 44-Pin 1016E-125LT44 1016E-100LJ 1016E-100LT44 PDF

    Untitled

    Abstract: No abstract text available
    Text: Lattica ispLSI 3192 ;Semiconductor I Corporation High Density Programmable Logic Functional Block Diagram Features HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    OCR Scan     		3192-100LM 240-Pin 3192-70LM 3192-70LMI PDF

    lattice 1016-60LJ

    Abstract: ispls11016 ispLSI1016 til 701 1016-60 Lattice 1016-80LJ 1016-80LJ loadable counter with timing diagram
    Text: Latticc ispLSI 1016 ; ; ; Semiconductor •■■ Corporation In-System Programmable High Density PLD Functional Block Diagram Features • HIGH-DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs


    OCR Scan     		Military/883 1016-80LT44 44-Pin 1016-60LJ 1016-60LT44 1016-60LJI 1016-60LT44I lattice 1016-60LJ ispls11016 ispLSI1016 til 701 1016-60 Lattice 1016-80LJ 1016-80LJ loadable counter with timing diagram PDF

    cd-rom circuit diagram

    Abstract: PT 10000
    Text: Lattice' ispLSI 3192 | Semiconductor I Corporation High Density Programmable Logic Functional Block Diagram Features HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    OCR Scan     		3192-100LM 240-Pin 3192-100LB272 272-Ball 3192-70LM 3192-70LB272 3192-70LMI cd-rom circuit diagram PT 10000 PDF

    Untitled

    Abstract: No abstract text available
    Text: L a tt Ì C e * i Coipo?at?ont0r ispLSr 2096E In-System Programmable SuperFAST High Density PLD Features Functional Block Diagram SUPERFA ST HIGH DENSITY IN-SYSTEM PRO GRAM MABLE LOGIC — — — — — 4000 PLD Gates 96 I/O Pins, Two Dedicated Inputs


    OCR Scan     		2096E 2096E 2096E-165LT128 128-Pin 2096E-165LQ128 2096E-135LT128 2096E-135LQ128 PDF

    Untitled

    Abstract: No abstract text available
    Text: Lattice ispLSr 1024 H I Semiconductor •■■ Corporation In-System Programmable High Density PLD Functional Block Diagram Features • HIGH-DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 4000 PLD Gates — 48 I/O Pins, Six Dedicated Inputs


    OCR Scan     		Military/883 1024-80LJ 68-Pin 1024-80LT 100-Pin 1024-60LJ 1024-60LT 1024-60LJI PDF