2 DECADE COUNTER Search Results

74HC-HCT390

Abstract: bcd decade counter ttl 74HC 74HCT
Contextual Info: 74HC/HCT390 MSI DUAL DECADE RIPPLE COUNTER FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-by-2,4, 5 ,1 0 ,2 0 ,2 5 , 50 or 100 • Two master reset inputs to clear each decade counter individually • Output capability: standard

L213N

Abstract: HEF4534B
Contextual Info: HEF4534B LSI REAL TIME 5-DECADE COUNTER The HEF4534B is a 5-decade ripple counter. The binary outputs of the decade counters are timemultiplexed by an internal scanner on four BCD outputs Oq to O 3 . The selected decade is indicated by a logic H IG H on the appropriate digit select output (OS q : units, 1; O S ): tens, 10; OS 2 : hundreds,

dual 4 bits decade counter

Abstract: 74LS390
Contextual Info: 74LS390 Signetics Counter Dual Decade Ripple Counter Product Specification Logic Products FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-by-2, 4, S, 10, 20, 25, 50 or 100 • Two Master Resets to clear each decade counter individually

74LS390

Contextual Info: Signetics 74LS390 Counter Dual Decade Ripple Counter Product Specification Logic Products FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-by-2, 4, 5, 10, 20, 25, 50 or 100 • Two Master Resets to clear each decade counter individually

Contextual Info: 74LS390 Signetics Counter Dual Decade Ripple Counter Product Specification Logic Products FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-by-2, 4, 5, 10, 20, 25, 50 or 100 • Two Master Resets to clear each decade counter individually

Contextual Info: Technical Data File Number CD54/74HC390 CD54/74HCT390 1838 High-Speed CMOS Logic Dual Decade Ripple Counter Type Features: • Two BCD decade or bi-quinary counters ■ One package can be configured to divide-by-2, 4, 5, 10, 20, 25, 50 or 100 • Two master reset inputs to clear each decade

74hct390

Contextual Info: Technical Data File Number CD54/74HC390 CD54/74HCT390 1838 High-Speed CMOS Logic Dual Decade Ripple Counter Type Features: • Two BCD decade or bi-quinary counters • One package can be configured to divide-by-2, 4, 5, 10, 20, 25, 50 or 100 • Two master reset inputs to clear each decade

Contextual Info: SN54290, SN54293, SN54LS290. SN54LS293, SN74290, SN74293, SN74LS290, SN74LS293 DECADE AND 4-BIT BINARY COUNTERS MARCH 1974 - REVISED MARCH 1988 '2 9 0 , 'LS290 . . . DECADE COUNTERS '293, 'LS293 . . . 4-B IT B IN A R Y COUNTERS SN5 4 2 9 0 , SN 54LS290, S N 54293,

74HCT390

Contextual Info: GD54/74HC390, GD54/74HCT390 DUAL 4-BIT DECADE COUNTERS General Description These devices are identical in pinout to the 54/74LS390. They incorporate two independent 4-Bit decade counters, each composed of a divideby-2 and a divide-by-5 counter. The divide-by-2 and

E17A

Abstract: synchronous counter using 4 flip flip HD74HC102 HD74HC161
Contextual Info: HD74HC160 HD74HC161 HD74HC162 HD74HC163 # HD74HC160-•• Synchronous Decade Counter D irect Clear # HD74HC161- Synchronous 4-bit Binary Counter (D irect Clear) # HD74HC1 6 2 "-Synchronous Decade Counter (Synchronous Clear) # HD74HC163 -Synchronous 4-bit Binary Counter (Synchronous Clear)

Contextual Info: MITSUBISHI LSTTLs M74LS390P DUAL DECADE COUNTER DESCRIPTION The M74LS390P is a semiconductor integrated circuit containing tw o asynchronous decade counters w ith direct reset inputs FEATURES • • • • • High mounting density w ith 2 circuits equivalent to

2025R

Contextual Info: LS TTL DN74LS Series DN74LS390 DN74LS390 Dual Decade Counters • Description DN74LS390 contains two asynchronous decade counter circuits with direct-coupled reset inputs. P-2 ■ Features • Includes two circuits corresponding to LS90 and LS290 for high-density mounting

Contextual Info: LS TTL DN74LS Series DN74LS390 DN74LS390 M74 ^ 39d Dual Decade Counters • Description P-2 DN74LS390 contains two asynchronous decade counter circuits with direct-coupled reset inputs. ■ Features • Includes two circuits corresponding to LS90 and LS290 for

DN74LS390

Abstract: LS290 LS90 MA161
Contextual Info: I LS TTL DN74LS Series DN74LS390 DN74LS390 Dual Decade Counters • Description P -2 D N74LS390 contains tw o asynchronous decade counter circuits w ith direct-coupled reset inputs. ■ Features • Includes tw o circuits corresponding to LS90 and LS290 for

DN74LS162A

Abstract: MA161
Contextual Info: LS TTL DN74LS Series DN74LS162A DN74LS162A Synchronous Decade Counters • Description DN74LS162A is a settable synchronous decade counter with synchronous reset input. ■ • • • • P-2 Features Synchronous reset and set inputs Carry output and enable input for cascade connection

Contextual Info: ¿4 0 2 -^ 1 5 i 4 0 ^ 5^ CD4026A, CD4033A Types CMOS Decade Counters/Dividers With Decoded 7-Segment Display Outputs and: Display Enable - CD4026A Ripple Blanking — CD4033A The RCA—CD4026A and CD4033A each consist o f a 5-stage Johnson decade counter

M74LS390P

Abstract: 20-PIN LS290 LS90 decade counter circuit diagram
Contextual Info: MITSUBISHI LSTTLs M74LS390P DUAL DECADE COUNTER DESCRIPTION The M74LS390P is a semiconductor integrated circuit containing tw o asynchronous decade counters w ith direct reset inputs PIN CONFIGURATION TOP VIEW CLOCK INPUT FEATURES • • • • • High mounting density w ith 2 circuits equivalent to

ICAN-6166

Abstract: CD4017A
Contextual Info: CD4017A Types CM O S Decade Counter/Divider its zero count. Use o f the Johnson decade oounter configuration perm its high speed operation, 2-input decim al decode gating, and spike-free decoded outputs. A n ti-lo ck gating is provided, thus assuring proper

HD74LS162

Abstract: 1S2074 74LSOO
Contextual Info: H D 7 4 LS1 6 2 •Synchronous Decade Counters synchronous clear This synchronous decade counter features an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so thet the outputs change coincident

400M

Abstract: DN74LS490 LS290 LS90
Contextual Info: I LS TTL DN74LS Series DN74LS490 DN74LS490 Dual 4 -bit Decade Counters • Description DN74LS490 contains two asynchronous decade counter circuits with direct coupled reset input and nine direct-coupled set inputs. P-2 ■ Features • Two circuits corresponding to LS90 and LS290 for high

cd4017 application

Abstract: sr flip flop CD4017 divide by 60 counter ICAN-6166 CD4017A CD4017 CD4017 gate diagram CD4017 features application of i CD4017 RCA-CD4017A
Contextual Info: CD4017A Types CMOS Decade Counter/Divider operation. 2-input decimal decode gating, and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper Plus 10 Decoded Decimal Outputs Johnson decade counter and an output de­ coder which converts the Johnson binary

DN74LS490

Abstract: LS290 LS90
Contextual Info: LS TTL DN74LS Series D N 74LS490 DN74LS490 ^ 74 ts 4q o Dual 4 - b it Decade Counters • Description P -2 D N 74LS490 contains tw o asynchronous decade counter circuits w ith direct coupled reset input an d nine direct-coupled set inputs. ■ Features •

Contextual Info: I LS TTL DN74LS Series DN74LS490 DN74LS490 Dual 4 -b it Decade Counters P-2 • Description DN74LS490 contains two asynchronous decade counter circuits with direct coupled reset input and nine direct-coupled set inputs. ■ Features • Two circuits corresponding to LS90 and LS290 for high

IC 74LS160

Abstract: cd40163b
Contextual Info: CD40160B# CD40161 Br CD40162«^ CD40163B Types CMOS Synchronous Programmable 4-Bit Counters High-Voltage T y p e s 2 0 -V o lt Rating CD 40160B — Decade w ith Asynchronous Clear CD 40161B — Binary with Asynchronous Clear CD 40162B — Decade with Synchronous