2*4 DECODER Search Results

DVB-S2

Contextual Info: AVC / H.264 and MPEG-2 HDTV / SDTV Integrated Receiver Decoder HVD6100 AVC / H.264 & MPEG-2 4:2:2 /4:2:0 IRD AVC / H.264 and MPEG-2 HDTV / SDTV Integrated Receiver Decoder IRD HVD6100 Multi-format IRD for AVC/H.264 and MPEG-2 4:2:2/4:2:0 HDTV/SDTV contribution and distribution with DVB-S2 demodulator

74LS247

Abstract: IC 74LS247 74ls248 74ls247 pin configuration SN74LS248 74ls249 54LS249
Contextual Info: M M O T O R O L A D E S C R I P T I O N - T h e S N 5 4 L S / 7 4 L S 2 4 7 thru S N 5 4 L S / 7 4 L S 2 4 9 are BCD-to-Seven-Segm ent Decoder/D rivers. The L S 2 4 7 and L 3 2 4 8 are functionally and electrically identical to the L S 4 7 and L S 4 8 w ith the sam e pinout configuration. The L S 2 4 9 is a

Contextual Info: June 1989 Semiconductor 5 4 4 2 A /D M 5 4 4 2 A /D M 7 4 4 2 A BCD to Decim al D eco ders Features • Diode clamped inputs ■ Also for application as 4-line-to-16-line decoders; 3-lineto-8-line decoders ■ All outputs are high for invalid input conditions

Contextual Info: SN54ALS29806, SN54ALS29809 SN74ALS29806, SN74ALS29809 COMPARATOR AND 2- TO 4-BIT DECODER D 2 9 3 4 , MARCH 1986 ALS29806 is a 6-Bit Identity Comparator Controlling a 2- to 4-Bit Decoder SN 54A LS29806 . . . JT PAC S N 7 4 A L S 2 9 8 0 6 . . DW OR NT TOP VIEW

74HC239

Abstract: C-239 SN74HC239
Contextual Info: SN54HC239, SN74HC239 DUAL 2-LINE TO 4 LINE DECODERS/DEMULTIPLEXERS D 2 8 0 4 . MARCH 1 9 8 4 -R E V IS E D SEPTEMBER 1987 • • S N 5 4 H C 2 3 9 . . . J P AC KAG E S N 7 4 H C 2 3 9 . . . D W OR N P A C K A G E TO P V IE W ! IG C 1 U 1A C 2 Incorporates 2 Enable Inputs to Simplify

CQ32

Abstract: 5442ADMQB 5442AFMQB DM5442AJ DM5442AW DM7442AN J16A N16E W16A cq325
Contextual Info: June 1989 Semi co n d u t o r 5 4 4 2 A /D M 5 4 4 2 A /D M 7 4 4 2 A BCD to Decim al D ecoders Features • Diode clamped inputs ■ Also for application as 4-line-to-16-line decoders; 3-lineto-8-line decoders ■ All outputs are high for invalid input conditions

Contextual Info: June 1989 5 4 4 2 A /D M 5 4 4 2 A /D M 7 4 4 2 A BCD to Decim al D ecoders General Description Features These BCD-to-decimal decoders consist of eight inverters and ten, four-input NAND gates. The inverters are connect­ ed in pairs to make BCD input data available for decoding

5442ADMQB

Abstract: 5442AFMQB DM5442AJ DM5442AW DM7442AN J16A N16E W16A
Contextual Info: June 1989 5 4 4 2 A /D M 5 4 4 2 A /D M 7 4 4 2 A BCD to Decim al D ecoders Features • D iode clam ped inputs ■ A lso fo r application as 4-line-to-16-line decoders; 3-lineto-8-line decoders ■ All outputs are high fo r invalid input conditions ■ Typical p ow er dissipation 140 mW

SN74L542

Abstract: LS42 SN5442A SN54LS42 SN7442A SN74LS42 J42A
Contextual Info: SN5442A, SN54LS42, SN7442A, SN74LS42 4-LINE BCD TO 10-LINE DECIMAL DECODERS SDLS109 MARCH Î9 7 4 —REVISED MARCH 193B All Outputs Are High for Invalid Input Conditions S N 5 4 4 2 A . S N 5 4 L S 4 2 . . , J OR W P A C K A G E SN 7442A . NPACKAGE S N 7 4 L S 4 2 . . . D O R N P AC K A G E

RVG4C

Abstract: sn74als29809
Contextual Info: SN54ALS29806, SN54ALS29809 SN74ALS29806, SN74ALS29809 COMPARATOR AND 2- TO 4-BIT DECODER D 2 93 4, M ARCH 1986 'A L S 2 9 8 0 6 is a 6-Bit Identity Comparator Controlling a 2- to 4-Bit Decoder S N 54A LS2 980 6 . . . J T PACKAGE S N 7 4 A L S 2 9 8 0 6 . . . DW OR NT P A C K A G E

74LS247N

Abstract: 74ls249n IC 74LS247 74ls247 pin configuration bcd to seven segment circuit diagram 74LS247 74LS248 DM54LS47 pin diagram of 74LS247 DM74LS248
Contextual Info: National Semiconductor DM54LS247/DM74LS247, DM54LS248/DM74LS248, DM54LS249/DM74LS249 BCD-to-Seven Segment Decoders/Drivers General Description Features The D M 5 4 L S 2 4 7 /D M 7 4 L S 2 4 7 a nd D M 5 4 L S 2 4 8 / D M 74LS 248 are e le c tric a lly and fu n ctio na lly id e n tica l to

SN54HC42

Abstract: SN74HC42 TT 46 N 16 LOF
Contextual Info: SN54HC42, SN74HC42 4 -LINE TO 10-LINE DECODERS 1-of-10 D 2 6 8 4 , D E C E M B E R 1 9 8 2 - R E V IS E D J U N E 1 9 8 9 • Full Decoding of Input Logic • All Outputs are High for Invalid BCD Conditions S N 5 4 H C 4 2 . . . J PACKAGE S N 7 4 H C 4 2 . . . D 1 OR N PACKAGE

74ALS29809

Abstract: LQ-520 74als29 AM29806 AM29809 SN74ALS29806 ALS29809 D2934 sn74als29809
Contextual Info: SN54ALS29806, SN54ALS29809 SN74ALS29806, SN74ALS29809 COMPARATOR AND 2 TO 4 BIT DECODER D 2 9 3 4 , M AR CH 1986 'A L S 2 9 8 0 6 is a 6 -B it Id e n tity C o m p a ra to r C ontrolling a 2 - to 4 -B it D ecod er S N 5 4 A L S 2 9 8 0 6 . . . J T P AC KA G E

lm628

Abstract: AN706 lm629 stt 128 AN-706 C1995 LM12 LM18293 dac0800 DC motor
Contextual Info: National Semiconductor Application Note 706 October 1993 Table of Contents 4 4 Initialization 1 0 INTRODUCTION 1 1 Application Note Objectives 1 2 Brief Description of LM628 629 2 0 DEVICE DESCRIPTION 2 1 Hardware Architecture 2 2 Motor Position Decoder 2 3 Trajectory Profile Generator

ic 74155

Abstract: applications of 74155 IC TTL 74155 74155 PIN DIAGRAM
Contextual Info: SN54155, SN54156, SN54LS155A. SN54LS156, SN74155, SN74156, SN74LS155A. SN74LS156 DUAL 2 UNE TO 4-LINE DECODERS/DEMULTIPLEXERS _ MARCH 1974 - REVISED MARCH 1988 Applications: Dual 2-to 4-Line Decoder Dual 1-to 4-Line Demultiplexer

Contextual Info: SN54HC42, SN74HC42 4 LINE TO 10-LIME DECODERS 1-oMO D 2 6 8 4 , D E C E M B E R 1 9 8 2 - R E V IS E D J U N E 1 9 8 9 S N 5 4 H C 4 2 . . . J P AC KA G E S N 7 4 H C 4 2 . . D * OR N P AC KA G E Full Decoding of Input Logic • All Outputs are High for Invalid BCD

ip00c

Contextual Info: IP00C811 IP00C811 Specifications INPUT 2 PORTS • 30-bit RGB/YUV 4:4:4 @ 166 MHz • 20-bit/10 bit YUV 4:2:2 @ 166 MHz EMBEDDED ANALOG FRONT-END • Video decoder for NTSC/PAL/SECAM • Supports Composite (CVBS) and S-Video inputs • 10-bit ADC • Adaptive Comb filter for Y/C separation

lS427

Abstract: sk341 LS42 SN5442A SN54LS42 SN7442A SN7444A SN74LS42 sn7444 4-LINE TO 10-LINE DECODERS with clock
Contextual Info: TYPES SN5442A THRU SN5444A, SN54L42 THRU SN54L44, SN54LS42, SN7442A THRU SN7444A, SN74LS42 4-LINE TO 10-LINE DECODERS 1 -O F-10 M ARCH 1974 - REVISED APRIL 19 8 5 '4 2 A , L 4 2 , L S 4 2 . . . B C D -T O -D E C IM A L '4 3 A , 'L 4 3 . . . E X C E S S -3 -T 0 -D E C IM A L

RCA-CD22101

Contextual Info: CMOS 4 x 4 x 2 Crosspoint Switches With Control Memory The RCA-CD22101 and CD22102 crosspoint switches consist of 4 x 4 x 2 arrays of crosspoints transmission gates , 4-line to 16-line decoders, and 16 latch circuits. Any one of the sixteen crosspoint pairs can be seiected

54HC154

Abstract: SN74HC154
Contextual Info: SN54HC154, SN74HC154 4-LINE TO 16 LINE DECODERS/DEMULTIPLEXERS 0 2 6 8 4 . DECEMBER 1 9 8 2 -R E V IS E D SEPTEMBER 1987 Decodes 4 Binary-Coded Inputs into One of 16 Mutually Exclusive Outputs S N 5 4 H C 1 5 4 . . . J T PACKAGE S N 7 4 H C 1 5 4 . . D W OR N T PACKAGE

16APSK

Abstract: DVB-S2 demodulator DVB-S2 Tuner demodulator HVD6100 demodulator dvb-s2 vcm HVE9100 DVB-S2 demodulator VCM NTT HVE9100 DVB-S2 32APSK
Contextual Info: HVD6100_フライヤー 英語版（W210 x H280mm）表 2009.3.24 AVC / H.264 and MPEG-2 HDTV / SDTV Integrated Receiver Decoder HVD6100 AVC / H.264 & MPEG-2 4:2:2 /4:2:0 IRD AVC / H.264 and MPEG-2 HDTV / SDTV Integrated Receiver Decoder IRD HVD6100

y12t

Contextual Info: PANASONIC IND L/ELEK -CIO 75 6 9 3 2 8 5 2 PANASONIC 1^32052 00070SS fl IN D L t EL EC T R O N I C , , . , ,? 2 C 07055 LS TTL DN74LSj>U—X _ D N 7 4 L S 1 5 4 / D N D T-66-21-55 dn74LS154/dn74LS1 54S 7 4 L S 1 5 4 S 4-line to 16-line Decoders/Demultiplexers

TMS44C256

Contextual Info: TMS44C256, TMS44C257 262,144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES JUNE 1 9 8 6 - • 2 6 2 ,1 4 4 X 4 Organization • Single 5-V Supply 10% Tolerance (TO P V IEW ) L 1 ^ 2 0 3 V SS 19 ] D Q 4 DQ2C 2 18 ] D Q 3 w [ 3 d q i Performance Ranges: TM S 4 4 C 2 5 _-1 0

AN9717

Abstract: ycbcr ycbcr to ycbcr 601 1334 ITU-R BT.601 "YCbCr to RGB" 22u smd BT.601 098B HMP8115
Contextual Info: Harris Semiconductor No. AN9717 Harris Multimedia March 1997 YCbCr to RGB Considerations Author: Keith Jack Introduction Converting 4:2:2 to 4:4:4 YCbCr Many video ICs now generate 4:2:2 YCbCr video data. The YCbCr color space was developed as part of ITU-R BT.601