1PD2 Search Results

MARKING G4G

Contextual Info: PRELIMINARY DATA SHEET_ MOS INTEGRATED CIRCUIT /1PD23C64000L 64M-BIT MASK-PROGRAMMABLE ROM 8M-WORD BY 8-BIT BYTE MODE / 4M-WORD BY 16-BIT(WORD MODE) Description The /xPD23C64000L is a 67,108,864 bits mask-programmable ROM. The word organization is selectable (BYTE

BF907

Abstract: QCPL hcnr201 spice model optocoupler spice model
Contextual Info: Wfipl m L ftm HEW LETT PACKARD High-Linearity Analog Optocouplers Technical Data HCNR200 HCNR201 Features Applications • Low Nonlinearity: 0.01% • K3 Ipd2/Ipdi Transfer Gain HCNR200: ± 15% HCNR201: ±5% • Low Gain Temperature Coefficient: -65 ppm/°C

Contextual Info: A K 9 3 C 4 7 S e rie s W ide Vcc 2.5V ~ 5.5V 1024 bit Serial Electrically Erasable PROM FEATURES •ADVANCED CMOS E2PROM TECHNOLOGY IREAD/WRITE NON-VOLATILE MEMORY —Wide Vcc (2.5V ~ 5.5V) operation — 1024 bits, 64 x 16 organization — Easy to use yet versatile serial data interface

stepping motor EM 323

Abstract: PD78213 em 154* "stepping motor" ZPD78213GQ-36 d78214 10000H D7821 PD78212 1NTC0 BT 815 transistor
Contextual Info: D A TA SHEET MOS INTEGRATED CIRCUIT ¿¿PD78212, 78213, 78214 8-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION The //PD78212,78213 and 78214 are 78K/H series products. The 78K/II series is an 8-bit single chip microcomputer which can access the memory space o f 1M byte with an external expansion.

AS11D

Contextual Info: SEC NEC Microcomputers, Inc. /¿PD2118 /¿PD2118-2 /XPD2118-3 16384 x 1 BIT DYNAMIC MOS RANDOM ACCESS MEMORY D E S C R IP T IO N The i¿PD2118 is a single +5V power supply, 16384 word by 1 bit Dynamic MOS RAM. The ¡1902] 18 achieves high speed with low power dissipation by the use of single tran­

Contextual Info: NEC pPD28C05 512 X 8-BIT CMOS E EPROM NEC Electronics Inc. Description Pin Configuration The juPD28C05 is an electrically erasable and program­ mable read-only memory EEPROM organized as 512 words by 8 bits. The device operates from a + 5-volt power supply and is fabricated w ith an advanced CMOS

alien h3

Abstract: epm7192s pin
Contextual Info: includes MAX 7000E& MAX 700OS M AX 7000 Programmable Logic Device Family July ^898, ver. 5.03 Features . . . S8 88 £8 S8 SSS H igh-perform ance, EEPROM -based p rogram m able logic devices PLDs based on second-generation M ultiple A rray MatriX (MAX)

74HC

Abstract: 7C344 CY7C344 CY7C344B LTAC01
Contextual Info: CY7C344 CY7C344B i f CYPRESS 32-Macrocell MAX EPLD Features Functional Description • High-performance, high-density re­ placement for TTL, 74HC, and cus­ tom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins

HXD BUZZER

Abstract: buzzer HXD 8K10
Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The ^PD78P083 A is a member of the ^P D /8 0 8 3 Subseries of the 78K/0 Series products. Comparing with the /1PD78P083 (standard), more strict quality assurance programs are applied to this product (called Special of the quality

Contextual Info: II s’ !' “ '• '■<: ! I, ! Il W ' j T. I /. I 'j li U 's ! >J o S1 ll , I /V 's . P R E L IM IN A R Y Figure 1. Block Diagram FBIN 'J GA1088 R E F C LK SO F1 FO GND ni nri m m m m rr 11-Output TES T Configurable Clock Buffer VD D QO Features GND * Q1

EP910PC-30

Abstract: EP910PC-40 EP910PC35 EP910PC-35 EP9100c EP910LC-30 EP910J EP910JC30 EP910LC-40 EP910JC-30
Contextual Info: EP910 HIGH-PERFORMANCE 24-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3187. OCTOBER 1988-REVISED AUQUST 1989 DUAL-IN-LINE PAC KA G E • High-Density (Over 900 Gates) Replacement for TTL and 74HC H O P VIEW) clk C 1 V_J40 39 iC 2 • Virtually Zero Standby Power. Typ 20 nA

Contextual Info: NEC N E C ELECTRONICS INC 3DE D • fci427SE5 0 0 2 5 3 1 4 3 ■ pPD7530x/31x/P308/P316 4-Bit Microcomputers With LCD Control ier/Driver NEC Electronics Inc. r- v t- n - w r - ‘+*1 - 1*1 '£-*i Description The pPD7530x/31x is a family of high-performance

transistor NEC D 882 p circuit diagram

Contextual Info: PRELIMINARY PRODUCT INFORMATION NEC MOS INTEGRATED CIRCUIT 16/8-BIT SINGLE-CHIP MICROCOMPUTER The ¿¿PD784031 is a product of the /¿PD784038 sub-series in the 78K/IV series. It contains various peripheral hardware such as RAM, I/O ports, 8-bit resolution A/D and D/A converters, timers, serial interface, and interrupt

D5AC32430

Abstract: D5AC312-30 D5AC312
Contextual Info: F e a tu re s G e Pie r a I . D e S C ri p t i o n Altera Corporation A-DS-312/324.01 High-performance EPLDs w ith 12 macrocells EP312 or 24 macrocells (EP324) - Combinatorial speeds as fast as 25 ns - Counter frequencies of up to 33.3 MHz - Pipelined data rates of up to 66 MHz

MC68HC05E6 equivalent

Abstract: MC68HC05E6 MC68HC705E6 Nippon capacitors
Contextual Info: MC68HC05E6/D MC68HC05E6 MC68HC705E6 TECHNICAL DATA < 3 M O T O R O L A INTRODUCTION MODES OF OPERATION AND PIN DESCRIPTIONS MEMORY INPUT/OUTPUT PORTS CORE TIMER PROGRAMMABLE TIMER A/D CONVERTER RESETS AND INTERRUPTS CPU CORE AND INSTRUCTION SET ELECTRICAL SPECIFICATIONS

MSI MS-5

Contextual Info: EPM 5032 EPLD Features H • ■ ■ ■ ■ High-speed, single-LAB MAX 5000 EPLD t PD as fast as 10 ns Counter frequencies up to 125 MHz Pipelined data rates up to 83 MHz 32 individually configurable macrocells 64 shareable expander product terms "expanders" allowing 68

DD131

Contextual Info: CY7C343 CY7C343B CYPRESS 64-Macrocell MAX EPLD Functional Description Features • 64 MAX macrocells in 4 LABs • 8 dedicated inputs, 24 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS E P R O M technology CY7C343

Contextual Info: CY7C342B S / CYPRESS Features • 128-Macrocell MAX EPLDs m a b lc L ogic D evice E P L D in w h ich C M O S E P R O M c e lls a re u se d to c o n fig u re logic fu n c tio n s w ith in th e d ev ice. T h e M A X a rc h ite c tu re is 100% u s e r c o n fig u r­

mc68hc05f5p

Abstract: 1117 asl CRYSTAL-16 001C 00FF M68HC05 MC68HC05F5FN 9111 asl 02 Nippon capacitors
Contextual Info: MC68HC05F5/D MC68HC05F5 TECHNICAL DATA M MOTOROLA MC68HC05F5 HCMOS MICROCONTROLLER UNIT Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,

transistor 9ct

Abstract: actel a1240 2 bit magnitude comparator 6562a Actel TPC 1280
Contextual Info: ACT 2 Field Programmable Gate Arrays Features • Up to 8000 Gate A rray Gates 20,000 P L D / L C A ™ equivalent gates • Replaces up to 210 T T L Packages • Replaces up to 69 20-Pin P A L Packages • Design Library with over 250 Macros • Single-Module Sequential Functions

IC 74ls244 latch

Contextual Info: MME D SIEMENS CMPNTSn OPTO S I E M E M B SB3b3Sb 000553b 5 HISIEX “T - 4 1 - •an HIGH EFFICIENCY RED S GREEN YELLOW IPD2545 IPD2547 IPD2548 .25" 4 Character 5x7 Dot Matrix, X-Y Stackable Industrial Alphanumeric Programmable Display with Built-in CMOS Control Functions

NEC D2716

Abstract: D2716 PD8048 PD2716 nec d2716 eprom uPD2716-2 NPD2 PD42S18160 iPD2716 ud271
Contextual Info: NEC f*PD2716 v' 1PD2716-2 NEC Electronics U.S.A. Inc. Microcomputer Division 16,384 2K X 8 BIT UV ERASABLE PROM D ESC RIP T IO N The /j P D 2 71 6 is a 16,384 bit (2048 x 8 bit) Ultraviolet Erasable and Electrically Pro­ grammable Read-Only Mem ory (E P R O M ). It operates from a single +5 volt supply,

M54922P

Abstract: 10KHZ 2804S m54922 PLL 2400 MHZ MITSUBISHI frequency counter ics
Contextual Info: M ITSUBISHI BIPOLAR DIGITAL ICs M54922P MITSUBISHI DGTL LOGIC 31E D • bSMTfla? OOlMTbb M ■MIT3; P L L F R E Q U E N C Y S Y N T H E S IZ E R FO R D IG ITA L TUNING S Y S T E M S T DESCRIPTION - i " ] - c 6 - q 5 PIN CONFIGURATIO N (TOP V IEW ) The M54922P is a semiconductor integrated circuit consisting

7C344-25

Abstract: Cypress cy7c344 CY7C344 74HC h55C Signal Path Designer
Contextual Info: CY7C344 CYPRESS 32-Macrocell MAX EPLD Features tional I/O pins communicate to one logic array block. In the CY7C344 LAB there are 32 macrocells and 64 expander prod­ uct terms. When an I/O macrocell is used as an input, two expanders are used to create an input path. Even if all of the