AN1064
Abstract: CY7C1380DV25 CY7C1380FV25 CY7C1382DV25 CY7C1382FV25
Text: CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 18-Mbit 512K x 36/1M x 18 Pipelined SRAM Functional Description [1] Features • Supports bus operation up to 250 MHz The CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/ CY7C1382FV25 SRAM integrates 512K x 36 and 1M x 18
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Original
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CY7C1380DV25,
CY7C1380FV25
CY7C1382DV25,
CY7C1382FV25
18-Mbit
36/1M
CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/
CY7C1382FV25
CY7C1380FV25
AN1064
CY7C1380DV25
CY7C1382DV25
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PDF
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AN1064
Abstract: CY7C1380DV25 CY7C1380FV25 CY7C1382DV25 CY7C1382FV25
Text: CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25 18-Mbit 512K x 36/1M x 18 Pipelined SRAM Functional Description [1] Features • Supports bus operation up to 250 MHz The CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/ CY7C1382FV25 SRAM integrates 512K x 36 and 1M x 18
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Original
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CY7C1380DV25,
CY7C1380FV25
CY7C1382DV25,
CY7C1382FV25
18-Mbit
36/1M
CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/
CY7C1382FV25
CY7C1380FV25
AN1064
CY7C1380DV25
CY7C1382DV25
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1381DV25 CY7C1383DV25 PRELIMINARY 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM Functional Description[1] Features • Supports 133-MHz bus operations The CY7C1381DV25/CY7C1383DV25 are 2.5V, 512K x 36 and 1M x 18 Synchronous Flowthrough SRAMs, respectively
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Original
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CY7C1381DV25
CY7C1383DV25
18-Mbit
36/1M
133-MHz
117-MHz
100-MHz
100-pin
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PDF
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AN1064
Abstract: CY7C1386DV25 CY7C1386FV25 CY7C1387DV25 CY7C1387FV25
Text: CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 18-Mbit 512K x 36/1M x 18 Pipelined DCD Sync SRAM Functional Description [1] Features • Supports bus operation up to 250 MHz The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/ CY7C1387FV25 SRAM integrates 512K x 36 and 1M x 18
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Original
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CY7C1386DV25,
CY7C1386FV25
CY7C1387DV25,
CY7C1387FV25
18-Mbit
36/1M
CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/
CY7C1387FV25
CY7C1386FV25
AN1064
CY7C1386DV25
CY7C1387DV25
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 18-Mbit 512K x 36/1M x 18 Pipelined DCD Sync SRAM Functional Description [1] Features • Supports bus operation up to 250 MHz The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/ CY7C1387FV25 SRAM integrates 512K x 36 and 1M x 18
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Original
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CY7C1386DV25,
CY7C1386FV25
CY7C1387DV25,
CY7C1387FV25
18-Mbit
36/1M
CY7C1386DV25/CY7C1387DV25
CY7C1387FV25
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PDF
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AN1064
Abstract: CY7C1381DV25 CY7C1381FV25 CY7C1383DV25 CY7C1383FV25
Text: CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM Functional Description [1] Features • Supports 133 MHz bus operations • 512K x 36/1M x 18 common IO • 2.5V core power supply (VDD) • 2.5V IO supply (VDDQ)
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Original
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CY7C1381DV25,
CY7C1381FV25
CY7C1383DV25,
CY7C1383FV25
18-Mbit
36/1M
CY7C1381DV25/CY7C1383DV25
100-pin
165-ball
AN1064
CY7C1381DV25
CY7C1381FV25
CY7C1383DV25
CY7C1383FV25
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1370CV25 CY7C1372CV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ The CY7C1370CV25 and CY7C1372CV25 are 2.5V, 512K x 36 and 1M x 18 Synchronous pipelined burst SRAMs with No
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Original
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CY7C1370CV25
CY7C1372CV25
36/1M
250-MHz
225-MHz
200-MHz
167-MHz
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PDF
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CY7C1370CV25
Abstract: CY7C1370CV25-167 CY7C1370CV25-200 CY7C1370CV25-225 CY7C1370CV25-250 CY7C1372CV25 CY7C1372CV25-225 CY7C1372CV25-250
Text: CY7C1370CV25 CY7C1372CV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ The CY7C1370CV25 and CY7C1372CV25 are 2.5V, 512K x 36 and 1M x 18 Synchronous pipelined burst SRAMs with No
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Original
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CY7C1370CV25
CY7C1372CV25
36/1M
CY7C1370CV25
CY7C1372CV25
CY7C13demnifies
CY7C1370CV25-167
CY7C1370CV25-200
CY7C1370CV25-225
CY7C1370CV25-250
CY7C1372CV25-225
CY7C1372CV25-250
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PDF
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CY7C1370CV25
Abstract: CY7C1370CV25-167 CY7C1370CV25-200 CY7C1370CV25-225 CY7C1370CV25-250 CY7C1372CV25 CY7C1372CV25-225 CY7C1372CV25-250 63a3
Text: CY7C1370CV25 CY7C1372CV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ The CY7C1370CV25 and CY7C1372CV25 are 2.5V, 512K x 36 and 1M x 18 Synchronous pipelined burst SRAMs with No
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Original
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CY7C1370CV25
CY7C1372CV25
36/1M
CY7C1370CV25
CY7C1372CV25
CY7C13k
CY7C1370CV25-167
CY7C1370CV25-200
CY7C1370CV25-225
CY7C1370CV25-250
CY7C1372CV25-225
CY7C1372CV25-250
63a3
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM Functional Description [1] Features • Supports 133 MHz bus operations • 512K x 36/1M x 18 common IO • 2.5V core power supply (VDD) • 2.5V IO supply (VDDQ)
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Original
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CY7C1381DV25,
CY7C1381FV25
CY7C1383DV25,
CY7C1383FV25
18-Mbit
36/1M
CY7C1381DV25/CY7C1383DV25
100-pin
165-ball
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PDF
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Untitled
Abstract: No abstract text available
Text: GS832118/32/36E-xxxV 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs Commercial Temp Industrial Temp Features Functional Description ct SCD Pipelined Reads The GS832118/32/36E-xxxV is a SCD Single Cycle Deselect pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
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Original
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GS832118/32/36E-xxxV
GS832118/32/36E-xxxV
8321Vxx
8321V18
8321xx
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PDF
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cypress AN1064 sram system guidelines
Abstract: CY7C1381D-133BZXI AN1064 CY7C1381D CY7C1381F CY7C1383D CY7C1383F n1033
Text: CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM Functional Description [1] Features • Supports 133 MHz bus operations • 512K x 36 and 1M × 18 common IO • 3.3V core power supply (VDD) • 2.5V or 3.3V IO supply (VDDQ)
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Original
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CY7C1381D,
CY7C1381F
CY7C1383D,
CY7C1383F
18-Mbit
36/1M
CY7C1381D/CY7C1383D
100-pin
165-ball
CY7C1381F/CY7C1383F
cypress AN1064 sram system guidelines
CY7C1381D-133BZXI
AN1064
CY7C1381D
CY7C1381F
CY7C1383D
CY7C1383F
n1033
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PDF
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cy7c1383f-100bgi
Abstract: AN1064 CY7C1381D CY7C1381F CY7C1383D CY7C1383F
Text: CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM Functional Description [1] Features • Supports 133 MHz bus operations • 512K x 36 and 1M × 18 common IO • 3.3V core power supply (VDD) • 2.5V or 3.3V IO supply (VDDQ)
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Original
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CY7C1381D,
CY7C1381F
CY7C1383D,
CY7C1383F
18-Mbit
36/1M
CY7C1381D/CY7C1383D
100-pin
165-ball
CY7C1381F/CY7C1383F
cy7c1383f-100bgi
AN1064
CY7C1381D
CY7C1381F
CY7C1383D
CY7C1383F
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PDF
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AN1064
Abstract: CY7C1381D CY7C1381F CY7C1383F
Text: CY7C1381D/CY7C1381F CY7C1383D/CY7C1383F 18 Mbit 512K x 36/1M x 18 Flow Through SRAM Features Functional Description • Supports 133 MHz bus operations ■ 512K x 36 and 1M × 18 common I/O ■ 3.3V core power supply (VDD) ■ 2.5V or 3.3V I/O supply (VDDQ)
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Original
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CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
36/1M
CY7C1381D/CY7C1381F
100-pin
165-ball
AN1064
CY7C1381D
CY7C1381F
CY7C1383F
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PDF
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Untitled
Abstract: No abstract text available
Text: Product Preview GS8320V18/32/36T-250/225/200/166/150/133 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 100-Pin TQFP Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Single Cycle Deselect SCD operation
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Original
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GS8320V18/32/36T-250/225/200/166/150/133
100-Pin
100-lead
GS8320V18/32/36T-250/225/200/166/150/133
8320V18
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PDF
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GS8320EV18
Abstract: GS8320EV18T-150 GS8320EV18T-166 GS8320EV18T-200 GS8320EV18T-225 GS8320EV32 GS8320EV36
Text: Product Preview GS8320EV18/32/36T-250/225/200/166/150/133 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 100-Pin TQFP Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Dual Cycle Deselect DCD operation
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Original
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GS8320EV18/32/36T-250/225/200/166/150/133
100-Pin
100-lead
8320EV18
GS8320EV18
GS8320EV18T-150
GS8320EV18T-166
GS8320EV18T-200
GS8320EV18T-225
GS8320EV32
GS8320EV36
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PDF
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A2-A20
Abstract: No abstract text available
Text: Preliminary GS832018/32/36T-250/225/200/166/150/133 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 100-Pin TQFP Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Single Cycle Deselect SCD operation
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Original
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GS832018/32/36T-250/225/200/166/150/133
100-Pin
100-lead
A2-A20
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PDF
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GS8320V18
Abstract: GS8320V18T-166 GS8320V18T-200 GS8320V18T-225 GS8320V32 GS8320V36
Text: Product Preview GS8320V18/32/36T-250/225/200/166/150/133 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 100-Pin TQFP Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Single Cycle Deselect SCD operation
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Original
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GS8320V18/32/36T-250/225/200/166/150/133
100-Pin
100-lead
Curr6/2003
8320V18
GS8320V18
GS8320V18T-166
GS8320V18T-200
GS8320V18T-225
GS8320V32
GS8320V36
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PDF
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GS832018
Abstract: GS832018T-225 GS832018T-250 GS832032 GS832036
Text: Product Preview GS832018/32/36T-250/225/200/166/150/133 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 100-Pin TQFP Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Single Cycle Deselect SCD operation
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Original
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GS832018/32/36T-250/225/200/166/150/133
100-Pin
100-lead
GS832018
GS832018T-225
GS832018T-250
GS832032
GS832036
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PDF
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CY7C1381CV25
Abstract: CY7C1383CV25
Text: CY7C1381CV25 CY7C1383CV25 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM Functional Description[1] Features • Supports 133-MHz bus operations The CY7C1381CV25/CY7C1383CV25 is a 2.5V, 512K x 36 and 1M x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with
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Original
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CY7C1381CV25
CY7C1383CV25
18-Mbit
36/1M
133-MHz
CY7C1381CV25/CY7C1383CV25
CY7C1381CV25/
CY7C1381CV25
CY7C1383CV25
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1370DV25 CY7C1372DV25 PRELIMINARY 18-Mbit 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ The CY7C1370DV25 and CY7C1372DV25 are 2.5V, 512K x 36 and 1M x 18 Synchronous pipelined burst SRAMs with No
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Original
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CY7C1370DV25
CY7C1372DV25
18-Mbit
36/1M
250-MHz
225-MHz
200-MHz
167-MHz
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1381CV25 CY7C1383CV25 18-Mb 512K x 36/1M x 18 Flow-Through SRAM Functional Description[1] Features • Supports 133-MHz bus operations The CY7C1381CV25/CY7C1383CV25 is a 2.5V, 512K x 36 and 1M x 18 Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with
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Original
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CY7C1381CV25
CY7C1383CV25
18-Mb
36/1M
133-MHz
117-MHz
100-MHz
100-pin
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PDF
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AN1064
Abstract: CY7C1381D CY7C1381F CY7C1383F
Text: CY7C1381D/CY7C1381F CY7C1383D/CY7C1383F 18 Mbit 512K x 36/1M x 18 Flow Through SRAM Features Functional Description • Supports 133 MHz bus operations ■ 512K x 36 and 1M × 18 common I/O ■ 3.3V core power supply (VDD) ■ 2.5V or 3.3V I/O supply (VDDQ)
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Original
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CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
36/1M
CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F
AN1064
CY7C1381D
CY7C1381F
CY7C1383F
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PDF
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CY7C1381D-100BGC
Abstract: CY7C1381D CY7C1383D
Text: CY7C1381D CY7C1383D PRELIMINARY 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM Functional Description[1] Features • Supports 133-MHz bus operations • 512K x 36/1M × 18 common I/O • 3.3V –5% and +10% core power supply (VDD) • 2.5V or 3.3V I/O supply (VDDQ)
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Original
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CY7C1381D
CY7C1383D
18-Mbit
36/1M
133-MHz
36/1M
100-MHz
100-pin
119-ball
CY7C1381D-100BGC
CY7C1381D
CY7C1383D
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PDF
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