18MBIT Search Results

hfdw

Contextual Info: _ ü 16/18Mbit 2Mx8/9 & 64/72Mbit (8Mx8/9) ConcurrentRDRAM Overview VDD GND BUSDATA[8] GND BUSDATA[7] (NC) BUSENABLE VDD BUSDATA[6] GND BUSDATA[5] VDDA RXCLK GNDA TXCLK VDD BUSDATA[4] GND BUSCTRL SIN VREF SOUT BUSDATA[3] GND BUSDATA[2] (NC)

TC59R1809

Contextual Info: High Speed Dynamic RAM Rambus DRAM Capacity Type No. Data Transfer Rats ns Organization Max Min Hit Latency (ns) Read Writs Power Power Supply (V) Dissipation (mW) No. of Pins 4.5MBit ‘ TC59R0409VK 524,288 x 9 2 5 48 16 5V±10% 1325 32 18MBit "TC59R1809VK

samsung concurrent rdram

Abstract: RDRAM CONCURRENT KM49RC2H-A60 samsung datecode rdram concurrent Samsung concurrent rdram concurrent RDRAM 72 RDRAM Clock concurrent rdram samsung
Contextual Info: Preliminary KM48 9 RC2H Concurrent RDRAM Overview Ordering Information The 16 / 18Mbit Concurrent Rambus DRAMs (RDRAM ) are Part No. Org. frequency by 8 or 9 bits. They are capable of bursting unlimited lengths of KM49RC2H-A53 2M x 9 533Mhz data at 1.5ns per byte (12.0ns per eight bytes). The use of Ram­

RDRAM CONCURRENT

Abstract: samsung concurrent rdram KM49RC2H-A66 km49rc2h-a60 km-48 concurrent RDRAM 72 KM49RC2H
Contextual Info: Preliminary Concurrent RDRAM KM48 9 RC2H 16/18Mbit R D R A M 2M X 8/9bit Concurrent RAMBUS DRAM Revision 0.7 February 1998 Rev. 0.7 (Feb. 1998) Preliminary Concurrent RDRAM KM48(9)RC2H Revision History Revision 0.5 (October 1997) - Preliminary • . Changed Peak TrasferRate from 700Mbps to 667Mbps. (page 1)

concurrent rdram

Abstract: RDRAM CONCURRENT es a 00112 concurrent rdram 72 mbit concurrent RDRAM 72 9 rambus concurrent rdram R64MC-50-600 SVP-32 rdram clock generator concurrent RDRAM 72
Contextual Info: Preliminary Information Concurrent RDRAM ® 16/18Mbit 2Mx8/9 & 64/72Mbit (8Mx8/9) RAMBUS Overview The 16/18/64/72-Mbit Concurrent Rambus DRAMs (RDRAM) are extremely high-speed CMOS DRAMs organized as 2M or 8M words by 8 or 9 bits. They are capable of bursting unlimited lengths of data at 1.67 ns

KM49RC2H-A60

Abstract: RDRAM CONCURRENT KM49RC2H samsung datecode samsung concurrent rdram RC2H-A66 concurrent RDRAM 72 9 concurrent rdram
Contextual Info: KM48RC2H/KM49RC2H Concurrent RDRAM 2M X 8 / 2 M x 9 Concurrent RDRAM Overview Ordering Information The 16 / 18Mbit Concurrent Rambus DRAMs RDRAM are Part No. Org. frequency KM49RC2H-A60 2M X 9 600Mhz extremely high-speed CMOS DRAMs organized as 2M words

Contextual Info: E2G1059-18-74 O K I Semiconductor This version: Jul. 1998 MSM5716C50/M SM 5718C50/ M D5764802 16M/18Mb 2M x 8/9 & 64Mb (8M x 8) Concurrent RDRAM DESCRIPTION The 1 6 /1 8 /64-M egabit C oncurrent Ram bus DRAMs (RDRAM ) are extrem ely hi'ghVspeed CMOS DRAMs organized as 2M or 8 M w ords by 8 or 9 bits. They are capable of bursting- linlimi ted

SOP 8 200MIL

Abstract: serial flash 256Mb fast erase spi TM 1628 IC SOP Micron 512MB NOR FLASH HN29V1G91T-30 HN58C1001FPI-15 M5M51008DFP-70HI 256mb EEPROM Memory CSP-48 TSOP 28 SPI memory Package flash
Contextual Info: Renesas Memory General Catalog 2003.11 Renesas Memory General Catalog Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with

GS8161Z18AT-300

Abstract: gs816
Contextual Info: Preliminary GS8161Z18/36AT-300/275/250/225/200 18Mb Pipelined and Flow Through Synchronous NBT SRAM Flow Through 2-1-1-1 1.8 V 2.5 V 300 345 300 340 275 320 275 315 250 295 250 285 230 265 225 260 mA mA mA mA tKQ tCycle 5.0 5.0 5.25 5.25 5.5 5.5 6.0 6.0 6.5

K8D3216UBC-pi07

Abstract: K5E5658HCM KAD070J00M KBH10PD00M K5D1257ACM-D090000 samsung ddr2 ram MTBF KBB05A500A K801716UBC k5d1g13acm k5a3281ctm
Contextual Info: Product Selection Guide Memory and Storage April 2005 MEMORY AND STORAGE SECTION A DRAM DDR2 SDRAM DDR SDRAM SDRAM RDRAM NETWORK DRAM MOBILE SDRAM GRAPHICS DDR SDRAM DRAM ORDERING INFORMATION FLASH NAND, OneNAND, NOR FLASH NAND FLASH ORDERING INFORMATION SRAM

CY7C1355C

Contextual Info: CY7C1355C, CY7C1357C 9-Mbit 256 K x 36 / 512 K × 18 Flow-Through SRAM with NoBL Architecture 9-Mbit (256 K × 36 / 512 K × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead

Contextual Info: CY7C1319KV18/CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth

Contextual Info: CY7C1163KV18/CY7C1165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • Separate independent read and write data ports

Contextual Info:  CY7C1143KV18/CY7C1145KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.0 Cycle Read Latency 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • Separate independent read and write data ports

CY7C1382DV33-200BZI

Contextual Info: CY7C1380DV33 CY7C1382DV33 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM Features Functional Description • Supports bus operation up to 200 MHz ■ Available speed grades is 200 MHz ■ Registered inputs and outputs for pipelined operation

Contextual Info: CY7C1148KV18/CY7C1150KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • 18-Mbit density (1 M x 18, 512 K × 36) With Read Cycle Latency of 2.0 cycles:

renesas tcam

Abstract: tcam renesas idt tcam Ayama 20000 cypress tcam Sahasra 50000 NSE sahasra Sahasra 50000 tcam tcam cypress
Contextual Info: CYNSE20512 CYNSE20256 PRELIMINARY Ayama 20000 Network Search Engine Family Data Sheet Features — QDR-II up to 250 MHz, Burst-of-2 and Burst-of-4 — Convenient “Clamshellable” pinout for ease of board design • Fast search rates — Up to 266 million searches per second MSPS in

Contextual Info: Datasheet PD44164095B-A μPD44164185B-A 18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION R10DS0016EJ0100 Rev.1.00 Dec 13, 2010 Description The μPD44164095B-A is a 2,097,152-word by 9-bit and the μPD44164185B-A is a 1,048,576-word by 18-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS sixtransistor memory cell.

Contextual Info: Datasheet PD44165084B-A μPD44165094B-A μPD44165184B-A μPD44165364B-A 18M-BIT QDRTM II SRAM 4-WORD BURST OPERATION R10DS0018EJ0100 Rev.1.00 Dec 13, 2010 Description The μPD44165084B-A is a 2,097,152-word by 8-bit, the μPD44165094B-A is a 2,097,152-word by 9-bit, the

CSR 8510

Abstract: CSR 8510 a10 CSR 8510 v4 80KSBR200 v8 doorbell wireless doorbell 813 doorbell circuit working ADS1118 2322 156 philips doorbell
Contextual Info: Advanced Datasheet 80KSBR200 sRIO SERIAL BUFFER FLOW-CONTROL DEVICE Device Overview ◆ The IDT80KSBR200 is a high speed Serial Buffer SerB that can connect to any Serial RapidIO compliant interface. This device is built to work with any sRIO device and especially with the IDT Pre-Processing

Contextual Info: CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1312KV18 – 1 M x 18

CYD01S36V

Abstract: CYD02S36V CYD04S36V CYD09S36V CYD18S36V 1.0mm pitch BGA
Contextual Info: CYD01S36V CYD02S36V/CYD04S36V CYD09S36V/CYD18S36V PRELIMINARY FLEx36TM 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM Features Functional Description • True dual-ported memory cells that allow simultaneous access of the same memory location The FLEx36 family includes 1-Mbit, 2-Mbit, 4-Mbit, 9-Mbit and

GS8162Z18B

Abstract: GS8162Z18BB-150 GS8162Z18BB-200 GS8162Z18BB-250 GS8162Z36B GS8162Z36BB-250
Contextual Info: GS8162Z18/36B B/D 18Mb Pipelined and Flow Through Synchronous NBT SRAM 119- & 165-Bump BGA Commercial Temp Industrial Temp Features • NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAM , NoBL™ and

GS8160ZV18CT

Abstract: GS8160ZV18CT-250 GS8160ZV18CT-300 GS8160ZV18CT-333
Contextual Info: Preliminary GS8160ZV18/36CT-333/300/250 100-Pin TQFP Commercial Temp Industrial Temp 18Mb Pipelined and Flow Through Synchronous NBT SRAM Features • NBT No Bus Turn Around functionality allows zero wait read-write-read bus utilization; Fully pin-compatible with