16JAN2004 Search Results

STM706P

Abstract: STM706R
Contextual Info: STM706T/S/R, STM706P, STM708T/S/R 3 V supervisor Features • Precision VCC monitor – STM706/708 T: 3.00 V ≤ VRST ≤ 3.15 V S: 2.88 V ≤ VRST ≤ 3.00 V R: STM706P: 2.59 V ≤ VRST ≤ 2.70 V RST and RST outputs ■ 200 ms typ trec ■ Watchdog timer - 1.6 s (typ)

STM690

Abstract: STM704 STM795 STM802 STM804 STM805 STM806
Contextual Info: STM690, STM704, STM795 STM802, STM804, STM805, STM806 3 V supervisor with battery switchover Features • RST or RST outputs ■ NVRAM supervisor for external LPSRAM ■ Chip enable gating STM795 only for external LPSRAM (7 ns max prop delay) ■ Manual (push-button) reset input

M20622

Abstract: m2062
Contextual Info: M2060/61/62 M2065/66/67 Preliminary Information Integrated Circuit Systems, Inc. VCSO FEC PLL FOR SONET/OTN GENERAL DESCRIPTION PIN ASSIGNMENT 9 x 9 mm SMT 27 26 25 24 23 22 21 20 19 FIN_SEL1 GND P_SEL2 DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC The M2060/61/62 and M2065/66/67 are VCSO (Voltage

817L

Abstract: 818l STM690A STM692A STM703 STM704 STM802 STM805 STM805L regulator 817 from ST
Contextual Info: STM690A, STM692A, STM703 STM704, STM802, STM805, STM817/8/9 5 V supervisor with battery switchover Features • 5 V operating voltage ■ NVRAM supervisor for external LPSRAM ■ Chip-enable gating STM818 only for external LPSRAM (7 ns max prop delay) ■

Contextual Info: 7 8 THIS DRAWING IS UNPUBLISHED. C COPYRIGHT 20 RELEASED FOR PUBLICATION - 6 5 4 3 2 20 LOC GP ALL RIGHTS RESERVED. LIGHT PIPE KIT 1761011-1 1 REVISIONS DIST 00 P LTR DESCRIPTION DATE DWN APVD E1 REVISED PER ECO-11-004835 18APR2011 RK HMR F REVISED PER ECO-114-000886

3348DC

Contextual Info: M29W400DT M29W400DB 4 Mbit 512 Kb x 8 or 256 Kb x 16, boot block 3 V supply Flash memory Features „ Supply voltage – VCC = 2.7 V to 3.6 V for Program, Erase and Read SO44 (M)(1) „ Access time: 45, 55, 70 ns „ Programming time – 10 s per byte/word typical

"NAND Flash"

Abstract: AN1793 NAND01GR3B NAND01GR4B NAND01GW3B NAND01GW4B NAND02GR3B NAND512W3B ST nand
Contextual Info: AN1793 APPLICATION NOTE How to Use the Chip Enable Don’t Care Option in Single Level Cell NAND Flash Memories This Application Note describes how to use the Chip Enable Don’t Care feature, which is available in both the NANDxxx-A and NANDxxx-B families of Single Level Cell SLC NAND Flash memories, and outlines

Contextual Info: STM705, STM706 STM707, STM708, STM813L 5 V supervisor Datasheet - production data • 200 ms typ trec  Watchdog timer - 1.6 s (typ) 8  Manual reset input (MR)  Power-fail comparator (PFI/PFO) 1  Low supply current - 40 A (typ)  Guaranteed RST (RST) assertion down to

STM705

Abstract: STM706 STM707 STM708 STM813L st mar 705
Contextual Info: STM705, STM706 STM707, STM708, STM813L 5 V supervisor Features • 5 V operating voltage ■ Precision VCC monitor – STM705/707/813L – 4.50 V ≤ VRST ≤ 4.75 V – STM706/708 – 4.25 ≤ VRST ≤ 4.50 V 8 1 SO8 M ■ RST and RST outputs ■ 200 ms (typ) trec

Contextual Info: STM706T/S/R, STM706P, STM708T/S/R 3 V supervisor Features • ■ Precision VCC monitor – STM706/708 T: 3.00 V ≤ VRST ≤ 3.15 V S: 2.88 V ≤ VRST ≤ 3.00 V R: STM706P: 2.59 V ≤ VRST ≤ 2.70 V 8 1 SO8 M RST and RST outputs ■ 200 ms (typ.) trec

automatic phase selector circuit diagram

Contextual Info: Preliminary Information Integrated Circuit Systems, Inc. M2040 FREQUENCY TRANSLATION PLL WITH AUTOSWITCH The M2040 is a VCSO Voltage Controlled SAW Oscillator based clock generator PLL designed for clock protection, frequency translation and jitter attenuation in fault tolerant

STM705

Abstract: STM706 STM707 STM708 STM813L
Contextual Info: STM705, STM706 STM707, STM708, STM813L 5 V supervisor Features • 5 V operating voltage ■ Precision VCC monitor – STM705/707/813L – 4.50 V ≤ VRST ≤ 4.75 V – STM706/708 – 4.25 ≤ VRST ≤ 4.50 V 8 1 SO8 M ■ RST and RST outputs ■ 200 ms (typ) trec

cc3041

Abstract: STM690 STM704 STM795 STM802 STM804 STM805 STM806 8n36 Voltage Supervisors
Contextual Info: STM690, STM704, STM795 STM802, STM804, STM805, STM806 3 V supervisor with battery switchover Features • RST or RST outputs ■ NVRAM supervisor for external LPSRAM ■ Chip enable gating STM795 only for external LPSRAM (7 ns max prop delay) ■ Manual (push-button) reset input

J-STD-020B

Abstract: M29W400D M29W400DB M29W400DT TFBGA48
Contextual Info: M29W400DT M29W400DB 4 Mbit 512Kb x8 or 256Kb x16, Boot Block 3V Supply Flash Memory FEATURES SUMMARY • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SUPPLY VOLTAGE – VCC = 2.7V to 3.6V for Program, Erase and Read ACCESS TIME: 45, 55, 70ns PROGRAMMING TIME

Contextual Info: STM690A, STM692A, STM703 STM704, STM802, STM805, STM817/8/9 5 V supervisor with battery switchover Features • 5 V operating voltage ■ NVRAM supervisor for external LPSRAM ■ Chip-enable gating STM818 only for external LPSRAM (7 ns max prop delay) ■

lcd dgl

Contextual Info: Fo r t une Semiconductor Corporation 富晶半導體股份有限公司 FS9912_LCS2 FS9912 standard code for 3,000 counts low cost scale application. Data Sheet TD-0410016 Rev. 1.5 This manual contains new product information. Fortune Semiconductor Corporation reserves the rights to

STM706P

Abstract: STM706R
Contextual Info: STM706T/S/R, STM706P, STM708T/S/R 3 V supervisor Features • ■ Precision VCC monitor – STM706/708 T: 3.00 V ≤ VRST ≤ 3.15 V S: 2.88 V ≤ VRST ≤ 3.00 V R: STM706P: 2.59 V ≤ VRST ≤ 2.70 V 8 1 SO8 M RST and RST outputs ■ 200 ms (typ.) trec

AN1793

Abstract: NAND01GR3B NAND01GR4B NAND01GW3B NAND01GW4B NAND02GR3B NAND512W3B 128Mbits nand256w3a
Contextual Info: AN1793 APPLICATION NOTE How to Use the Chip Enable Don’t Care Option in Single Level Cell NAND Flash Memories This Application Note describes how to use the Chip Enable Don’t Care feature, which is available in both the NANDxxx-A and NANDxxx-B families of Single Level Cell SLC NAND Flash memories, and outlines

Contextual Info: M29W400DT M29W400DB 4 Mbit 512Kb x8 or 256Kb x16, Boot Block 3V Supply Flash Memory FEATURES SUMMARY • SUPPLY VOLTAGE Figure 1. Packages – VCC = 2.7V to 3.6V for Program, Erase and Read ■ ACCESS TIME: 45, 55, 70ns ■ PROGRAMMING TIME – 10µs per Byte/Word typical

lcd dgl

Abstract: FS9912 93C46 LP 93C46 S-81230 LOAD CELL 16 bit ADC low cost FS9912_LCS2 4x14mm dgl lcd lb2h
Contextual Info: Fo r t une Semiconductor Corporation 富晶半導體股份有限公司 FS9912_LCS2 FS9912 standard code for 3,000 counts low cost scale application. Data Sheet TD-0405004 Rev. 1.4 This manual contains new product information. Fortune Semiconductor Corporation reserves the rights to

706S

Abstract: STM706P STM706R MARKING SO8
Contextual Info: STM706T/S/R, STM706P, STM708T/S/R 3 V supervisor Features • Precision VCC monitor – STM706/708 T: 3.00 V ≤ VRST ≤ 3.15 V S: 2.88 V ≤ VRST ≤ 3.00 V R: STM706P: 2.59 V ≤ VRST ≤ 2.70 V 1 SO8 M ■ RST and RST outputs ■ 200 ms (typ.) trec ■

Contextual Info: STM690, STM704, STM795 STM802, STM804, STM805, STM806 3 V supervisor with battery switchover Features • RST or RST outputs ■ NVRAM supervisor for external LPSRAM ■ Chip enable gating STM795 only for external LPSRAM (7 ns max prop delay) ■ Manual (push-button) reset input

mr 818 diode

Abstract: STM690A STM692A STM703 STM704 STM802 STM805 STM805L 6n38 817l
Contextual Info: STM690A, STM692A, STM703 STM704, STM802, STM805, STM817/8/9 5 V supervisor with battery switchover Features • 5 V operating voltage ■ NVRAM supervisor for external LPSRAM ■ Chip-enable gating STM818 only for external LPSRAM (7 ns max prop delay) ■

M29W400D

Abstract: JESD97 M29W400DB M29W400DT TFBGA48
Contextual Info: M29W400DT M29W400DB 4 Mbit 512 Kb x 8 or 256 Kb x 16, boot block 3 V supply Flash memory Features • Supply voltage – VCC = 2.7 V to 3.6 V for Program, Erase and Read ■ Access time: 45, 55, 70 ns ■ Programming time – 10 µs per byte/word typical