167MHZ Search Results

Contextual Info: K7N803645M K7N801845M 256Kx36 & 512Kx18 Pipelined NtRAMTM Document Title 256Kx36 & 512Kx18-Bit Pipelined NtRAM TM Revision History History Draft Date Remark 0.0 1. Initial document. September. 1997 Preliminary 0.1 1. Changed speed bin from 167MHz to 150MHz

K7n801845m

Contextual Info: K7N803645M K7N801845M 256Kx36 & 512Kx18 Pipelined NtRAMTM Document Title 256Kx36 & 512Kx18-Bit Pipelined NtRAM TM Revision History History 1. Initial document. Draft Date September. 1997 Remark Preliminary 0.1 1. Changed speed bin from 167MHz to 150MHz 2. Changed DC Parameters;

ZZ 160 ITT

Abstract: 36/ZZ 160 ITT
Contextual Info: KM736S849 KM718S949 PRELIMINARY 256Kx36 & 512Kx18 Pipelined NfRAM Document Title 256KX36 & 512Kx18-Bit Pipelined NfRAM™ Revision Historv R ev. No. H isto rv Draft Date R em ark 0.0 1. Initial document. September. 1997 Prelim inary 0.1 1. Changed speed bin from 167MHz to 150MHz

Contextual Info: KM736S849 KM718S949 256Kx36 & 512Kx18 Pipelined NtRAMTM Document Title 256Kx36 & 512Kx18-Bit Pipelined NtRAM TM Revision History History 1. Initial document. Draft Date September. 1997 Remark Preliminary 0.1 1. Changed speed bin from 167MHz to 150MHz 2. Changed DC Parameters;

capacitor selection

Abstract: effect of parasitic in capacitors
Contextual Info: Application Bulletin AB-8 Power Supply Bypass Capacitor Selection Capacitor Selection Most of the energy in digital pulses lies in the area below Fknee, where: Fknee = 0.5 tr and tr is signal rise-time. For IsoLoop Isolators: Fknee = 0.5 = 167MHz 3 x10-9 This frequency may be considered the analog “bandwidth” of the device.

DSO751SR

Abstract: DSO321SR
Contextual Info: SMD Crystal Oscillators DSO221SR/DSO321SR/DSO531SR/DSO751SR •Features ● Low current consumption: 8mA max 167MHz, 3.3V ● Low voltage operation: 1.8V/2.5V/2.8V/3.3V ● Offers Narrow deviation: ±20x10−6/±30×10−6/±50×10−6/±100×10−6 ● Available up to 167MHz by using AT cut fundamental

Contextual Info: KM736S849 KM718S949 256Kx36 & 512Kx18 Pipelined NtRAMTM Document Title 256Kx36 & 512Kx18-Bit Pipelined NtRAM TM Revision History History Draft Date Remark 0.0 1. Initial document. September. 1997 Preliminary 0.1 1. Changed speed bin from 167MHz to 150MHz 2. Changed DC Parameters;

84154

Abstract: CY37128P84-125JI
Contextual Info: fax id: 6146 Ultra371 28 UltraLogic 128-Macrocell ISR™ CPLD High speed Feat u res - W x = • 128 m acrocells in eight logic blocks 167MHz — tpo = 6.5 ns • In-System R e p ro g ra m m ab le ISR™ — ts = 3.5 ns — JTAG com plia nt on board p rogram m in g

Contextual Info: SMD Crystal Oscillators DSO221SR/DSO321SR/DSO531SR/DSO751SR •Features ● Low current consumption: 8mA max 167MHz, 3.3V ● Low voltage operation: 1.8V/2.5V/2.8V/3.3V ● Offers Narrow deviation: ±20x10−6/±30×10−6/±50×10−6/±100×10−6 ● Available up to 167MHz by using AT cut fundamental

50REF

Contextual Info: KM736S849 KM718S949 256Kx36 & 512Kx18 Pipelined NtRAMTM Document Title 256Kx36 & 512Kx18-Bit Pipelined NtRAM TM Revision History History Draft Date Remark 0.0 1. Initial document. September. 1997 Preliminary 0.1 1. Changed speed bin from 167MHz to 150MHz 2. Changed DC Parameters;

No Turnaround RAM

Contextual Info: KM736S849 KM718S949 PRELIMINARY 256Kx36 & 512Kx18 Pipelined NtRAMTM Document Title 256Kx36 & 512Kx18-Bit Pipelined NtRAM TM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. September. 1997 Preliminary 0.1 1. Changed speed bin from 167MHz to 150MHz

Contextual Info: KM736S849 KM718S949 PRELIMINARY 256Kx36 & 512Kx18 Pipelined NfRAM Document Title 256KX36 & 512Kx18-Bit Pipelined NfRAM™ Revision History Rev. No. Historv Draft Date Remark 0.0 1. Initial document. September. 1997 Prelim inary 0.1 1. Changed speed bin from 167MHz to 150MHz

K7N801845M

Abstract: K7N803645M
Contextual Info: K7N803645M K7N801845M 256Kx36 & 512Kx18 Pipelined NtRAMTM Document Title 256Kx36 & 512Kx18-Bit Pipelined NtRAM TM Revision History History 1. Initial document. Draft Date September. 1997 Remark Preliminary 0.1 1. Changed speed bin from 167MHz to 150MHz 2. Changed DC Parameters;

Contextual Info: KM736S849 KM718S949 256Kx36 & 512KX18 Pipelined NfRAM D o c u m e n t T itle 256Kx36 R e v is io n & 512Kx18-Bit Pipelined NfRAM™ H is io r v Historv Draft Date Remark 0.0 1. Initial document. September. 1997 Preliminary 0.1 1. Changed speed bin from 167MHz to 150MHz

ee94

Contextual Info: CRYSTAL CONTROLLED ran OSCILLATORS SURFACE MOUNT 3.3V PECL AURORA, IL 60505 PHONE 6 3 0 8 5 1 -4 7 2 2 FAX (63 0) 8 5 1 -5 0 4 0 www.conwin.com CONNOR W IN F IE L D EE94—51* SPECIFICATIONS Frequency Range E E 94-52* 13MHz to 167MHz 13MHz to 200MHz ±25ppm

LQFP-100

Contextual Info: TOSHIBA TC55WD1618FF-133,-150,-167 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT TENTATIVE SILICON GATE CMOS 1,048,576-WORD BY 18-BIT SYNCHRONOUS NO-TURNAROUND STATIC RAM DESCRIPTION The TC55WD1618FF is a synchronous static random access memory SRAM organized as 1,048,576 words by

Contextual Info: ADS809 ADS 809 www.ti.com 12-Bit, 80MHz Sampling ANALOG-TO-DIGITAL CONVERTER TM FEATURES DESCRIPTION ● DYNAMIC RANGE: SNR: 65dB at 10MHz fIN SFDR: 68dB at 10MHz fIN The ADS809 is a high-dynamic range 12-bit, 80MHz pipelined Analog-to-Digital A/D converter. It includes a

C6701

Contextual Info: TMS320C6701 FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR SPRS067E – MAY 1998 – REVISED MAY 2000 D Highest Performance Floating-Point Digital D D D D D Signal Processor DSP TMS320C6701 – 8.3-, 6.7-, 6-ns Instruction Cycle Time – 120-, 150-, 167-MHz Clock Rate

RJP 30 h1

Contextual Info: TMS320C6713B FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 D Highest-Performance Floating-Point Digital D D D D D D Signal Processor DSP : TMS320C6713B − Eight 32-Bit Instructions/Cycle − 32/64-Bit Data Word

Contextual Info: SM320C6711ĆEP, SM320C6711BĆEP, SM320C6711CĆEP, SM320C6711DĆEP FLOATINGĆPOINT DIGITAL SIGNAL PROCESSORS SGUS054A − AUGUST 2004 − REVISED SEPTEMBER 2005 D Controlled Baseline D D D D D D D D L1/L2 Memory Architecture − One Assembly/Test Site, One Fabrication

bzx 850

Abstract: bzx 850 30
Contextual Info: CY7C1412AV18 CY7C1414AV18 36 Mbit QDR II SRAM Two Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses

C6000

Abstract: TMS320C6000 TMS320C6411
Contextual Info: TMS320C6411 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS196I − MARCH 2002 − REVISED JUNE 2005 D Low-Cost, High-Performance Fixed-Point D D D D DSP − TMS320C6411 − 3.33-ns Instruction Cycle Time − 300-MHz Clock Rate − Eight 32-Bit Instructions/Cycle

9l reset

Abstract: CY7C0852V-133AC CY7C09289V CY7C09369V CY7C09379V
Contextual Info: CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM CY7C0851V/CY7C0852V CY7C0831V/CY7C0832V 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM Features Functional Description

K7A323600M

Abstract: K7B321825M-QC65 K7A321800M
Contextual Info: K7A323600M K7A321800M 1Mx36 & 2Mx18 Synchronous SRAM Document Title 1Mx36 & 2Mx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial draft May. 10. 2001 Advance 0.1 1. Add 165FBGA package Aug. 29. 2001 Preliminary