13OUTPUT Search Results

Contextual Info: ANALOG DEVICES Mixed-Signal Processor with Host Interface Port ADSP-21 msp50A/55A/56A FEATURES 77 ns Instruction Cycle Time from 13.00 MHz Crystal ADSP-2100 Family Code & Function Compatible 2K Words of On-Chip Program Memory RAM 1K Words of On-Chip Data Memory RAM

ADSP-2187L

Contextual Info: ANALOG DEVICES FEATURES PERFORMANCE 19 ns Instruction Cycle Tim e @ 3.3 V olts, 52 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture A llow s Dual Operand Fetches in Every Instruction Cycle M ultifunction Instructions

Contextual Info: JÄN 1 7 1992 DSP Microcomputer with Host Interface Port ADSP-2111 ANALOG ► DEVICES FUNCTIONAL BLOCK DIAGRAM FEATURES Complete DSP Microcomputer 60 ns Instruction Cycle Time from 16.67 MHz Crystal ADSP-2100 Family Code & Function Compatible 2K Words of On-Chip Program Memory RAM

KD 2107

Abstract: driver circuit for irs 2110 C7172 PCS-60 STC transistors g135 arm 272432 1HT1 N80c186
Contextual Info: INTEL CORP UP/PRPHLS bflE ]> • HÖ2bl7S G13SÖ37 176 M I T L l in te l 80C186EA/80C188EA AND 80L186EA/80L188EA 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS ■ 80C186 Upgrade for Power Critical Applications ■ Fully Static Operation ■ True CMOS Inputs and Outputs

Contextual Info: £ Z 7 ^ 7/ SG S "T H O M S O N R LKgTTMDtEi ESM1600B QUAD COMPARATOR INTERFACE CIRCUIT . MINIMUM HYSTERESIS VOLTAGE AT EACH INPUT: 0.3V • OUTPUT CURRENT : 15 mA . LARGE SUPPLY VOLTAGE RANGE : + 10V to + 35V ■ INTERNAL THERMAL PROTECTION . INPUT AND OUTPUT CLAMPING PROTEC­

TAD71

Contextual Info: ANALOG DEVICES Multi-Port Internet Gateway Processor Preliminary Technical Data ADSP-21mod970 FEATURES Performance • Complete Single-Chip Multi-Port Internet Gateway Processor N o External Memory • Implements Six M odem Channels in One Package Required

ADSP-2185N

Abstract: ADSP-2100 ADSP-2184N ADSP-2186N ADSP-2187N ADSP-2189M ADSP-2188
Contextual Info: a DSP Microcomputer ADSP-218xN Series PERFORMANCE FEATURES 12.5 ns Instruction Cycle Time @1.8 V Internal , 80 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle

TA8654N

Abstract: TRF1060 TA8654
Contextual Info: TOSHIBA TENTATIVE Unit: itim 1-CHIP NTSC C T V SYSTEM TA8654N combines all the functions ' required for an NTSC color TV system in a 64-lead, dual-in-line shrink-type 1.78 mil plastic package. This device is designed to offer wide capability of application from fundamental CTV to a

TSE 4041

Abstract: ADSP-21msp56a PGA300 msp50 ADSP-21msp55A ADSP-21msp50 001C 27C64 80C51 HA20
Contextual Info: ► ANALOG DEVICES Mixed-Signal Processor with Host Interface Port ADSP-21 msp50A/55A/56A FEATURES 77 ns Instruction Cycle Time from 13.00 MHz Crystal ADSP-2100 Family Code & Function Compatible 2K Words of On-Chip Program Memory RAM 1K Words of On-Chip Data Memory RAM

3845b

Abstract: EC35-3c8 uc3844b application note 850C PJ3844 PJ3844B PJ3845 PJ3845B core ferroxcube 23-SOFT-START
Contextual Info: T PJ3844B / PJ3845B High Performance Current Mode Controller he PJ3844B , PJ3845 series are high performance fixed cycle-by-cycle current limiting , programmable output frequency current mode controllers. This is specifically deadtime, and a latch for single pulse metering. Allowing

strain guage

Abstract: C3189 4 bit barrel shifter circuit for left shift dsp 32 c processor adsp 218x user manual AD1847 ADSP-2100 ADSP-2181 ADSP2185L ADSP-2185L
Contextual Info: a FEATURES PERFORMANCE 19 ns Instruction Cycle Time @ 3.3 Volts, 52 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions

pcst 2103

Contextual Info: PREO DflO NA lIRr 80C186EA/80C188EA AND 80L186EA/80L188EA 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS • 80C186 Upgrade for Power Critical Applications ■ Fully Static Operation ■ True CMOS Inputs and Outputs Integrated Feature Set ■ Speed Versions Available 3V :

Contextual Info: in te l. 80C186EA20, 16, 12 16-BIT HIGH INTEGRATION EMBEDDED PROCESSOR • 80C186 Upgrade for Power Critical Applications ■ Full Static Operation ■ True CMOS Inputs and Outputs Integrated Feature Set — Static 186 CPU Core — Power Save, Idle and Powerdown

ADSP-2185N

Abstract: ADSP-2100 ADSP-2184N ADSP-2186N ADSP-2187N ADSP-2189M D1881 ca144
Contextual Info: a DSP Microcomputer ADSP-218xN Series PERFORMANCE FEATURES 12.5 ns Instruction Cycle Time @1.8 V Internal , 80 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle

proton rx 4000 watts power amplifier circuit diagram

Abstract: RCA-CD401 cd22014 ICAN-6362 vogt 545 44 vogt inductor j9 570 17 013 20 RCA-CD4046B common cathode 7 SEGMENT DISPLAY LT 543 CD22014E CD22011
Contextual Info: RCA COS/MOS Integrated Circuits This DATABOOK contains complete technical information on RCA stand­ ard commercial COS/MOS integrated circuits. It covers the full line of RCA standard A- and B-series digital logic circuits, special-function circuits crosspoint switches and level shifters ,

intel PLCC packaging draw

Abstract: PLCC 68 intel package dimensions 80C186 intel end 80C187 80L188EA13 INTEL PLCC 68 dimensions 0000110w
Contextual Info: Intel 80C186EA/80C188EA AND 80L186EA/80L188EA 16-Bit High-Integration Embedded Processors Datasheet • ■ ■ Intel® 80C186 Upgrade for Power Critical Applications Fully Static Operation True CMOS Inputs and Outputs Product Features ■ ■ Integrated Feature Set

Contextual Info: • Q ö l b ö O Q O Q M D Ö Ö b bHfl ■ ANA A N A LO G D EV ICES □ A N AL OG D E V I C E S INC bSE D . DSP Microcomputer ADSP-2101 1.1 Scope. This specification covers the detail requirements for a monolithic CMOS 16-bit fixed-point DSP microcomputer.

ADSP-2185N

Abstract: MN1280-R ADSP-2100 ADSP-2184N ADSP-2186N ADSP-2187N ADSP-2189M
Contextual Info: a DSP Microcomputer ADSP-218xN Series PERFORMANCE FEATURES 12.5 ns Instruction Cycle Time @1.8 V Internal , 80 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle

Contextual Info: □ ANALOG DEVICES Mixed-Signal Processors with Host Interface Ports ADSP-21 msp50A/55A/56A FEATURES 77 ns Instruction Cycle Time from 13.00 MHz Crystal ADSP-2100 Family Code & Function Compatible 2K Words of On-Chip Program Memory RAM IK Words of On-Chip Data Memory RAM

Contextual Info: A N A LO G D E V IC E S Dual, 12-Bit, 40 MSPS MCM A/D Converter with Analog Input Signal Conditioning AD10242 FEATURES Two Matched ADCs with Input Signal Conditioning Selectable Bipolar Input Voltage Range ±0.5 V, ±1.0 V, ±2.0 V Full MIL-STD-883B Compliant

diode ed 85

Abstract: 010BSC
Contextual Info: PJ3845B High Performance Current Mode Controller T he PJ3845B series is high performance fixed frequency cycle-by-cycle current limiting , programmable output current mode controllers. This is specifically designed deadtime, and a latch for single pulse metering. Allowing

21D12

Abstract: CCITT V.90
Contextual Info: ANALOG DEVICES Multi-Port Internet Gateway Processor Preliminary Technical Data ADSP-21mod970 FEATURES Performance • C om plete S in gle-C h ip M ulti-Port Internet G atew ay P rocessor N o External M em ory • Im plem ents S ix M od em C hannels in One Package

80c187

Contextual Info: 80C186EA/80C188EA, 80L186EA/80L188EA INTRODUCTION Unless specifically noted, all references to the 80C186EA apply to the 80C188EA, 80L186EA, and 80L188EA. References to pins that differ between the 80C186EA/80L186EA and the 80C188EA/ 80L188EA are given in parentheses. The “ L" in the

800 WATT MOSFET AMPLI DIAGRAM

Abstract: EC35-3c8 PJ3842B Core Ferroxcube EC35-3C8 PJ3842BCD PJ3842BCS 27-MOSFET Ferroxcube 3C8 flyback fly back trans EC35 12v
Contextual Info: PJ3842B High Performance Current Mode Controller he PJ3842B series is high performance fixed frequency T Also included are protective features consisting of input current mode controllers. This is specifi cally designed and reference undervoltage lockouts each with hysteresis,