PAL VIHH programming pulse
Abstract: 10L8 12L6 14L4 16C1 16L2 16L8 16R8 PAL10H8 PAL 16L2
Text: SECTION 2 Programmable Array Logic PAL Data Sheets National Semiconductor Description The PAL fa m ily u tiliz e s N a tio n a l S e m ic o n d u c to r ’s S c h o ttk y T TL p ro c e s s and b ip o la r PROM fu s ib le -lin k te c h n o lo g y to p ro v id e
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04through
PAL VIHH programming pulse
10L8
12L6
14L4
16C1
16L2
16L8
16R8
PAL10H8
PAL 16L2
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palasm
Abstract: HAL 16L8 MONOLITHIC MEMORIES ZHAL10H8A ZHAL10L8A ZHAL12H6A ZHAL12L6A ZHAL14H4A ZHAL14L4A ZHAL16C1A ZHAL16H2A
Text: Zero Power CMOS Hard Array Logic ZHAL 20A Series Patent Pending Features/ Benefits Ordering Information • Zero standby power • 25-ns maximum propagation delay PART NUMBER PACKAGE ARRAY OUTPUTS REG COMB • HC and HCT compatible • Space saving PLCC available
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25-ns
20-pin
16L8/16R8/16R6/16R4
ZHAL20A
palasm
HAL 16L8 MONOLITHIC MEMORIES
ZHAL10H8A
ZHAL10L8A
ZHAL12H6A
ZHAL12L6A
ZHAL14H4A
ZHAL14L4A
ZHAL16C1A
ZHAL16H2A
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16R8A
Abstract: No abstract text available
Text: Zero Power CMOS Hard Array Logic ZHAL 20A Series Features/ Benefits Ordering Information • Zero standby power PART NUMBER • 25-ns maximum propagation delay PACKAGE ARRAY OUTPUTS COMB REG • HC and HCT compatible • Space saving PLCC available • Low power alternative for Small and Medium 20-pln PAL
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25-ns
20-pln
16L8/16R8/16R6/16R4
ZHAL10H8A
ZHAL12H6A
ZHAL14H4A
ZHAL16H2A
ZHAL16C1A
ZHAL10L8A
ZHAL12L6A
16R8A
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16R8A
Abstract: 16H2A
Text: Zero Power CMOS Hard Array Logic ZHAL 20A Series Ordering Information Features/ Benefits • Zero standby power PART NUMBER • 25-rw maximum propagation delay PACKAGE ARRAY OUTPUTS COMB REG • HC and HCT compatible • Space tavlng PLCC available • Low power alternative lor Small and Medium 20-pln PAL«
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25-rw
20-pln
16L8/16R8/16R6/16R4
ZHAL10H8A
ZHAL12H6A
ZHAL14H4A
ZHAL16H2A
ZHAL16C1A
ZHAL10L8A
ZHAL12L6A
16R8A
16H2A
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16A4
Abstract: 16L8 16R4 16R6 16R8 16X4 L6C1
Text: Data Sheets SECTION 2 2 9 National Semiconductor Program m able Array Logic PAL Description The PAL® fam ily utilizes National Sem icon d u cto r’s S chottky TTL process and bipolar PROM fu sib le -lin k tech n o lo g y to provide user-program m able logic to replace conven
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Untitled
Abstract: No abstract text available
Text: Programmable Array Logic PAL Description The PAL® family utilizes National Semicon ductor’s Schottky TTL process and bipolar PROM fusible-link technology to provide user-programmable logic to replace conven tional SSI/MSI gates and flip-flops. Typical
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