1036B Search Results

2SB883

Contextual Info: Ordering number:1036B PNP/NPN Epitaxial Planar Silicon Darlington Transistors 2SB883/2SD1193 Driver Applications Applications Package Dimensions • Motor drivers, printer hammer drivers, relay drivers, voltage regulator control. unit:mm 2022A [2SB883/2SD1193]

SD1193

Abstract: 2SB883 2SD1193 2SD119
Contextual Info: O rd e rin g n u m b e r : EN 1036B 2SB883/2SD1193 PNP/NPN Epitaxial Planar Silicon Darlington Transistors Driver Applications A pplications •Motor drivers, printer hammer drivers, relay drivers, voltage regulator control. F eatu re s • High DC current gain.

416-ball

Abstract: 1152-ball 132-ball lattice fpbga 484 FPBGA
Contextual Info: Product Bulletin April 2009 #PB1240H Lattice Ordering Guidelines for Custom Product and Tape and Reel Introduction Lattice “Custom Products” include the following: • Factory Programming • Custom Processing • Custom Testing • Custom Marking •

AL437

Abstract: L97c L235C L103T L41C L140C L94C l165c L239C L43C
Contextual Info: ORCA ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC November 2003 Preliminary Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSPI4 FPSC contains two

L130C

Abstract: L74c l31c l97c l65c A311TC l146c l48c L202C L235C
Contextual Info: ORCA ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC May 2009 Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSPI4 FPSC contains two

84 pin plcc lattice dimension

Abstract: C045
Contextual Info: Package Diagrams November 2003 16-Pin Plastic DIP Package Dimensions in Inches -BN/2 b1 1 WITH LEAD FINISH E 5 6 CL E1 c1 c N SEE DETAIL A BASE METAL (b) SECTION Z-Z CL BASE PLANE c 5 -A- D 6 eA Z Z 4 A2 A eB 7 -C.015 SEATING PLANE A1 L b2 10 b .010 GAGE

TCAM

Abstract: Silicon Access Networks 2AMCC
Contextual Info: H i g h-P er for ma nce P ac ket P ro cess or iFlow Packet Processor Product Brief iFlow Packet Processor www.siliconaccess.com DESCRIPTION The iFlow™ Packet Processor iPP is a highperformance 20Gbps, multithreaded, wire-speed packet processor capable of 30 million packets per second.

ST6C

Abstract: triacs BT 412 132DA
Contextual Info: ST62T00 ST62T01, E01 8-BIT OTP/EPROM MCUs WITH A/D CONVERTER 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency • -40 to +85°C Operating Temperature Range ■ Run, Wait and Stop Modes ■ 5 Interrupt Vectors ■ Look-up Table capability in OTP/EPROM

d1684

Abstract: 84-Pin QFN FCBGA304 1704B MachXO2 Family Lattice Semiconductor Package Diagrams 256-Ball fpBGA 132-ball 284-BA x45e2
Contextual Info: Package Diagrams November 2012 Data Sheet 20-Pin 300-Mil CERDIP Package Dimensions in Inches (DATUM A) B N/2 1 4 E E1 N E3 e/2 E DETAIL A D A 4 BASE PLANE (DATUM B) A2 A1 A C SEATING PLANE e b2 Z b .010 M L Z E2 C A B b1 (c) 4X WITH LEAD FINISH c1 BASE METAL

D48X

Abstract: 11 ak 30 a4
Contextual Info: Package Diagrams October 2004 16-Pin Plastic DIP Package Dimensions in Inches -BN/2 b1 1 WITH LEAD FINISH 5 E 6 CL E1 c1 c N SEE DETAIL A BASE METAL (b) SECTION Z-Z CL BASE PLANE -A- D c 5 6 eA Z Z 4 A2 A eB 7 -CSEATING PLANE .015 A1 L b2 10 b .010 GAGE

X3230

Abstract: ORT82G5 P802 AT T ORCA fpga OIF-SPI4-02 SPI42
Contextual Info: F I E L D P R O G R A M M A B L E S Y S T E M - O N - A - C H I P ORCA ORSPI4 Embedded SPI4.2 Core, 3.7Gbps SERDES, High-Speed Memory Controller + FPGA Introducing the ORCA ORSPI4, the next-generation FPSC from Lattice Semiconductor. The ORSPI4 device offers a fast

14.5M 1982

Abstract: AC12 MO-220 MO-275 ANSI Y14.5 FCBGA304 fcbga-304 ansi-y14.5m-1982 LAttice bottom marking SCM40
Contextual Info: Package Diagrams November 2010 Data Sheet 20-Pin 300-Mil CERDIP Package Dimensions in Inches (DATUM A) B 1 N/2 4 E E1 N E3 e/2 E DETAIL A D A 4 BASE PLANE (DATUM B) A2 A1 A C SEATING PLANE e b2 Z b .010 M L E2 C A B b1 (c) 4X WITH LEAD FINISH c1 BASE METAL

L47C

Abstract: L146C L135 l54c L62C L97C verilog code of prbs pattern generator L71C L235C L43C
Contextual Info: ORCA ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC February 2005 Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSPI4 FPSC contains two

bc 106

Abstract: EC20 LFEC20E-4F672C ORSPI4-2FE1036C RD1019 Verilog DDR memory model
Contextual Info: QDR Memory Controller May 2005 Reference Design RD1019 Introduction QDR SRAM is a new memory technology defined by a number of leading memory vendors for high-performance and high-bandwidth communication applications. QDR is a synchronous pipelined burst SRAM with two separate

Lattice Semiconductor Package Diagrams 256-Ball fpBGA

Abstract: LAttice top marking BB 1704 672-BALL SCM40 AC12 MO-220 MO-275 84 pin plcc lattice dimension fcbga-304
Contextual Info: Package Diagrams October 2011 Data Sheet 20-Pin 300-Mil CERDIP Package Dimensions in Inches (DATUM A) B N/2 1 4 E E1 N E3 e/2 E DETAIL A D A 4 BASE PLANE (DATUM B) A2 A1 A C SEATING PLANE e b2 Z b .010 M L Z E2 C A B b1 (c) 4X WITH LEAD FINISH c1 BASE METAL

Contextual Info: 1 123456789A7BC36DDEF3ED7 477B771 1 1 1 1 1  !1 "# $1B3D%3B1"9%124%3 &" "21 69D5371 CD%C+1 4,-64B3 1 634EBDA31 54B41 ,93,BD91 DBC9-B1 C-A41 DB363BD91 D1 D633771

317 jrc

Abstract: jrc 5532 dd jrc 317 transistor pcr 406 st6203b st62t00b jrc 319 thermistor PCR 406 jrc 11 CONNECTOR CENTRONIC 34 pin
Contextual Info: ST62T00 ST62T01, E01 8-BIT OTP/EPROM MCUs WITH A/D CONVERTER PRODUCT PREVIEW 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency • -40 to +85°C Operating Temperature Range ■ Run, Wait and Stop Modes ■ 5 Interrupt Vectors ■ Look-up Table capability in OTP/EPROM

BC 106

Contextual Info: QDR Memory Controller May 2004 Reference Design RD1019 Introduction QDR SRAM is a new memory technology defined by a number of leading memory venders for high-performance and high-bandwidth communication applications. QDR is a synchronous pipelined burst SRAM with two separate

C5611 Transistor

Abstract: transistor c5578 M96639 7809a C5611 c5578 C5701 C5562 27611A C5762
Contextual Info: RoHS Compliance – Complete Listing As of Monday, April 28, 2008 10:22 AM The compliance date shown indicates the date Belden’s internal specifications were changed. Material manufactured prior to the compliance date may still be in stock at Belden facilities and in our

JRC 072 D

Contextual Info: {= *7 Æ 7 , S G S -T H O M S O N S T6200B liïilO Ê IM JIlL IM n M lliü lD têi S T6201B 8-BIT HCMOS MCUs WITH A/D CONVERTER • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +85°C Operating Temperature Range

ET 321

Contextual Info: rZ * ]§ J , ST62T00 ST62T01, E01 S G S -T H O M S O N BSflDg^SHHUKgiriMlKlQlgi 8-BIT OTP/EPROM MCUs WITH A/D CONVERTER • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +85°C Operating Temperature Range

ORT82G5

Abstract: P802
Contextual Info: F I E L D P r o g r a m m a b le s y s t e m - o n - a - c h ip ORCA ORSPI4 Embedded SPI4.2 Core, 3.7Gbps SERDES, High-Speed Memory Controller + FPGA Introducing the ORCA ORSPI4, the next-generation FPSC from Lattice Semiconductor. The ORSPI4 device offers a fast

L211C

Abstract: 3100B L17c R68T l71c
Contextual Info: ORCA ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC July 2004 Preliminary Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSPI4 FPSC contains two

L43C

Abstract: L130C l44c L239C l220c L235C L97c L62C L81C l31c
Contextual Info: ORCA ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC October 2007 Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSPI4 FPSC contains two