10115 ECL Search Results

signetics 10115

Abstract: 10115N 10115 ecl 10115F signetics+10115
Contextual Info: 10115 Signetics Line Receiver Quad Differential Line Receiver Product Specification ECL Products DESCRIPTION The 10115 is a Quad Differential Line Receiver intended for use in sensing signals over long lines. The base Refer­ ence Bias Voltage Vbb makes the de­

10115N

Contextual Info: Philips Components-Signetics 10115 Document No. 853-0650 ECN No. 99799 Line Receiver Date of Issue June 14, 1990 Status Product Status Quad Differential Line Receiver ECL Products FEATURES • Typical propagation delay: 2.0ns • Typical supply current H ee

10115N

Contextual Info: Philips Components 10115 Document No. 8 5 3 -0 6 5 0 ECN No. 99799 Date of Issue June 14, 1990 Status Product Status Line Receiver Quad Differential Line Receiver ECL Products FEATURES ORDERING INFORMATION • Typical propagation delay: 2.0ns • Typical supply current H

op07

Abstract: wt32 D5555 op09 cross SHARP I A05 FR30 MB91F127 MB91F128 SCR deta sheet RD-146
Contextual Info: FUJITSU SEMICONDUCTOR CM71-10115-1E CONTROLLER MANUAL FR30 32-BIT MICROCONTROLLER MB91F127/128 HARDWARE MANUAL FR30 32-BIT MICROCONTROLLER MB91F127/128 HARDWARE MANUAL FUJITSU LIMITED PREFACE • Objectives and Intended Readers Thank you very much for using our semiconductor products.

95H28

Abstract: 9582 Fairchild 95H28 Fairchild 9582 10631 flip-flop oa 9505 ecl 9528 11C06 11C58 95H29
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-ECL E21 11C58 E22 9582 E23 95115/10115/10515 9 5 (8)4 cx 1 1 - .¡¿ .1 4 2 Q Vex INPUT FILTER — (14) 10 ( 13)9 7 (11) 6 (10) (16) 12 ( 1) 13 15 (3) 14 (2) 14 BIAS FILTER 12 13 13 3 (7) 2 (6) U 0 -6 11 (15)

95H28

Abstract: 95H29 9582 Fairchild 11C58 9528 Fairchild 9582 95H28 Fairchild
Contextual Info: FAIRCHILD LO GIC/CO NN ECTIO N DIAGRAMS DIGITAL-ECL E21 11C58 E22 9582 E23 95115/10115/10515 cx 9 5 (8)4 1 1 -.¡¿.1 4 3 (7) 2 (6) E24 95116/10114/10116 10514/10516 (9 )5 (8)4 (10)6 2 Q Vex INPUT FILTER — (14) 10 (13)9 7 (11 ) 6 (10) (16 ) 12 (1) 13

9582 ECL

Abstract: 9582 Fairchild 95H28 GI 9528 ecl 9528 95H28 Fairchild 11C58 8T26 8T28 95H29
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-ECL E21 11C58 E22 9582 E23 95115/10115/10515 9 5 (8)4 cx 1 1 - .¡¿ .1 4 3(7) 2(6) E24 95116/10114/10116 10514/10516 (9)5 (8)4 (10)6 2 Q Vex INPUT FILTER — (14) 10 (13)9 7(11) 6(10) (16) 12 (1) 13 15(3) 14(2)

9582 Fairchild

Abstract: 95H28 11C44 11C58 11C24 95H29 E106 MOS Clock Driver 9582 95H28 Fairchild
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-ECL E21 11C58 E22 9582 E23 95115/10115/10515 9 5 (8)4 cx 1 1 - .¡¿ .1 4 2 Q Vex INPUT FILTER — (14) 10 ( 13)9 7 (11) 6 (10) (16) 12 ( 1) 13 15 (3) 14 (2) 14 BIAS FILTER 12 13 13 3 (7) 2 (6) U 0 -6 11 (15)

95H28

Abstract: 11C70 95H29 11C58 9582 Fairchild 95H28 Fairchild
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-ECL E21 11C58 E22 9582 E23 95115/10115/10515 9 5 (8)4 cx 1 1 - .¡¿ .1 4 3(7) 2(6) E24 95116/10114/10116 10514/10516 (9)5 (8)4 (10)6 2 Q V ex INPUT FILTER — (14) 10 (13)9 7(11) 6(10) (16) 12 (1) 13 15(3)

9582 Fairchild

Abstract: f 9582 dc 9582 dc 9582 ECL ecl 9528 Fairchild 9582 ECL 9582 10116 11C58 8T13
Contextual Info: F A IRCH ILD L O G IC /C O N N E C T IO N D IA G R A M S DIGITAL-ECL E21 11C58 E22 9582 E23 95115/10115/10515 cx 9 5 (8)4 1 1 -.¡¿.1 4 3 (7) 2 (6) E24 95116/10114/10116 10514/10516 (9 )5 (8)4 (10)6 2 Q Vex INPUT FILTER — (14) 10 (13)9 7 (11 ) 6 (10)

9582 Fairchild

Abstract: Fairchild 9582 9582 ECL 10114 10115 ecl 100114 10116 RECEIVER ECL logic Fairchild 96106
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER Power Dissipation mW (Typ) tpd (ns) (Typ) Number Receivers per Package ±1 No ECL -5 .2 250 2.2 3 6B 9627 Dual R S 232/ M IL Std 188 Line Receiver 9616 45 ±25 No TTL ±12 234 70 2 6B.9B.3I 10014* Active Termination

signetics 10107

Abstract: decoder active high outputs signetics 10131 ECL 10131 ECL 10102 ECL 10105
Contextual Info: LANSDALE SEMICONDUCTOR bOE J> I 5 3 ^ 3 0 3 O O O Q S m 0^3 « L T E Rating Supply Voltage - Vcc Input Voltage - Vjn SIGNETICS INTEGRATED CIRCUITS Output Source Current 10K ECL Storage Temperature Range Emitter-coupled logic is the fastest logic technology available

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quad TTL to MECL Translator M C I 012 4 The M C 10124 is a quad translator tor interfacing data and control signals between a saturated logic section and the M ECL section ot digital systems. The M C 10124 has TTL compatible inputs, and M EC L complementary open-em itter

9627DM

Abstract: TTL 7404 propagation delay 9582 Fairchild 9N04/7404 9582 ECL Fairchild 9582 7404 DIP fairchild 7404 DTL Fairchild 9627DC
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER tpd ns (Typ) Number Receivers per Package No ECL -5 .2 250 2.2 3 6B 9627 Dual RS 232/ MIL Std 188 Line Receiver 9616 45 ±25 No TTL ±12 234 70 2 6B.9B.3I 10014* Active Termination All ECL Logic VREF NA No ECL -5 .2 -

UA1489

Abstract: IBM-370 MA1488
Contextual Info: FAIRCHILD INTERFACE LINE DRIVERS/RECEIVERS/TRANSCEIVERS Output Current mA Typ Power Dissipation mW (Typ) Drivers per Package Logic/Connection Diagram(s) Package(s) Quad /uA1489 TTL Volt Single Ended ±10 220 ±15 — 4 I49 6A.9A 2 54/7437 Quad 2NAND Any

Contextual Info: FAIRCHILD INTERFACE LINE DRIVERS/RECEIVERS/TRANSCEIVERS Output Current mA Typ Power Dissipation mW (Typ) Drivers per Package Logic/Connection Diagram(s) Package(s) Quad /uA1489 TTL Volt Single Ended ±10 220 ±15 — 4 I49 6A.9A 2 54/7437 Quad 2NAND Any

F10014

Abstract: ECL Handbook F10506 ECL 200 F10105 f10107 F10-100 f10504
Contextual Info: F10014 ACTIVE TERMINATOR F10K VOLTAGE COMPENSATED ECL G E N ER A L D ESC R IP TIO N — The F10014 Is a voltage com pensated ECL circuit w h ich replaces discrete diode clam ping circuits at considerable reduction in cost, board space and power dissipation. It operates from the standard - 5 . 2 V ECL

Fairchild 9614

Abstract: Fairchild 9615 JM38510 Fairchild 9582 Fairchild 9614 line driver 9614
Contextual Info: FAIRCHILD INTERFACE LINE DRIVERS/RECEIVERS/TRANSCEIVERS Drivers per Package Logic/Connection Diagram s Package(s) 4 I49 6A.9A 10 +5 0 108 4 D2 3I, 6A,9A 48 13 +5 0 98 4 D2 3I, 6A,9A Single Ended 48 11 +5 0 52 2 D5 3I, 6A.9A Volt Single Ended 48 70 +5 0 88

MC10525L

Abstract: C101 MC10102 MC10103 MC10105 MC10106 MC1011 MC10110 MC10114 MC10115
Contextual Info: M E C L 1 0 .0 0 0 se m e s INTEGRATED CIRCUITS FROM MOTOROLA M C 1 0 , 1 0 0 /1 0 ,2 0 0 Series - 3 0 to + 8 5 ° C WIC10 ,5 0 0 /1 0 ,6 0 0 Series ( - 5 5 to + 1 2 5 ° C ) C irc u it design w ith M E C L 1 0 ,0 0 0 is unusually con­ venient. The d iffe re n tia l a m p lifie r in p u t and e m itterfo llo w e r o u tp u t p e rm it high fa n o u t, th e w ired-O R o p tio n ,

t25 dc he nv

Contextual Info: ECL PRODUCT INFORMATION Test Voltage Values V v ih a MIN Vil a MAX -30 °C +25°C +85°C -0.890 -0.810 -0.700 -1.890 -1.850 -1.825 -1.205 -1.105 -1.035 -1.500 -1.475 -1.440 PARAMETER LOW LEVEL OUTPUT VOLTAGE LOW LEVEL VOH (V) HIGH LEVEL V0 LA <V> THRE8HOLD

Contextual Info: □ □ □ ADH -050 AND ADH-051 ILC D A TA DEVICE CORPORATION HYBRID VIDEO TRACK/HOLD 100 ns Acquisition Time; ± 0.0125% Max Linearity Error FEATURES DESCRIPTION The industry's first hybrid video track

1883B

Contextual Info: B Q ILC DATA DEVICI MONOBRID ADH-030 II CORPO RATION ! 12 BIT 35NSEC HYBRID D/A CONVERTER High Reliability; One Monolithic Active Component FEA T U R ES • FA S T : 35 N SEC S E T T LIN G • HIGH R E L IA B IL IT Y : 3,000,000 HOUR M T B F DESCRIPTION APPLICATIONS

MC10100

Abstract: C101 MC10102 MC10103 MC10105 MC10106 MC1011 MC10110 MC10114 MC10115
Contextual Info: MECL 10.000 semes INTEGRATED CIRCUITS FROM MOTOROLA MC10,100/10,200 Series -30 to +85°C WIC10,500/10,600 Series (-55 to +125°C) C irc u it design w ith M E C L 1 0 ,0 0 0 is u nusually con­ venient. The d iffe re n tia l a m p lifie r in p u t and e m itte rfo llo w e r o u tp u t p e rm it high fa n o u t, th e w ired-O R o p tio n ,

NL412

Abstract: MC10101L C101 MC10102 MC10103 MC10105 MC10106 MC1011 MC10110 MC10114
Contextual Info: M E C L 1 . 0 s e m e s INTEGRATED CIRCUITS FROM MOTOROLA MC10,100/10,200 Series -30 to +85°C WIC10,500/10,600 Series (-55 to +125°C) C irc u it design w ith M E C L 1 0 ,0 0 0 is u nusually con­ venient. The d iffe re n tia l a m p lifie r in p u t and e m itte rfo llo w e r o u tp u t p e rm it high fa n o u t, th e w ired-O R o p tio n ,