PLL 100Mhz
Abstract: 5V2528 IDT5V2528
Text: IDT5V2528/A 2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE 2.5V / 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER FEATURES: • • • • The IDT5V2528 inputs, PLL core, Y0, Y1, and FBOUT buffers operate from the 3.3V VDD and AVDD power supply pins.
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IDT5V2528/A
IDT5V2528
5V2528
5V2528A
PLL 100Mhz
5V2528
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MG802C256Q
Abstract: DS06 MOSYS QFP-1420 MG802C256
Text: MG802C256 Ultra Low Latency, High Performance MOSYS 256Kx32 SGRAM Preliminary Information Features • • • • • • • • • • • • • • • SGRAM protocol High bandwidth 100MHz-166MHz operation Reduced Latency Improved critical timing parameter limits
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MG802C256
256Kx32
100MHz-166MHz
256Kx32
100-pin
MG802C256Q
DS06
MOSYS
QFP-1420
MG802C256
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5V2528
Abstract: IDT5V2528
Text: IDT5V2528/A 2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE 2.5V / 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER FEATURES: • • • • The IDT5V2528 inputs, PLL core, Y0, Y1, and FBOUT buffers operate from the 3.3V VDD and AVDD power supply pins.
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IDT5V2528/A
IDT5V2528
5V2528
5V2528A
5V2528
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Untitled
Abstract: No abstract text available
Text: IDT5V2528/A 2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE 2.5V / 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER IDT5V2528/A PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES OCTOBER 28, 2014 FEATURES: • • • • PLL core, Y0, Y1, and FBOUT buffers operate from the 3.3V VDD and AVDD power
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IDT5V2528/A
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IDT5V2528
Abstract: 5V2528 5V2528A
Text: IDT5V2528/A 2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE 2.5V / 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER FEATURES: • • • • The IDT5V2528 inputs, PLL core, Y0, Y1, and FBOUT buffers operate from the 3.3V VDD and AVDD power supply pins.
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IDT5V2528/A
IDT5V2528
5V2528
5V2528A
5V2528
5V2528A
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Untitled
Abstract: No abstract text available
Text: IDT5V2528/A 2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE 2.5V / 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER FEATURES: • • • • The IDT5V2528 inputs, PLL core, Y0, Y1, and FBOUT buffers operate from the 3.3V VDD and AVDD power supply pins.
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IDT5V2528/A
100MHz
166MHz:
150ps
133MHz
25MHz
140MHz
167MHz
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5V2528
Abstract: IDT5V2528
Text: IDT5V2528/A 2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE 2.5V / 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER FEATURES: • • • • The IDT5V2528 inputs, PLL core, Y0, Y1, and FBOUT buffers operate from the 3.3V VDD and AVDD power supply pins.
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IDT5V2528/A
IDT5V2528
5V2528
5V2528A
5V2528
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Untitled
Abstract: No abstract text available
Text: IDT5V2528/A 2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE 2.5V / 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER IDT5V2528/A NRND NOT RECOMMENDED FOR NEW DESIGNS FEATURES: • • • • PLL core, Y0, Y1, and FBOUT buffers operate from the 3.3V VDD and AVDD power
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IDT5V2528/A
100MHz
166MHz:
150ps
133MHz
25MHz
140MHz
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Untitled
Abstract: No abstract text available
Text: IDT5V2528/A 2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE 2.5V / 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER The IDT5V2528 inputs, PLL core, Y0, Y1, and FBOUT buffers operate from the 3.3V VDD and AVDD power supply pins. One bank of ten outputs provide low-skew, low-jitter copies of CLK. Of
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IDT5V2528/A
IDT5V2528
5V2528
5V2528A
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qfp 32 land pattern
Abstract: qfp 64 0.4 mm pitch land pattern maxim qfp marking
Text: ❖ MG802C256 Ultra Low Latency, High Performance M oSys 6 256Kx32 SGRAM im m a ry Features ssssasses& ssssa SGRAM protocol High bandwidth 100MHz-166M Hz operation Reduced Latency Improved critical timing parameter limits 2 Internal Banks for hiding Row Precharge
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OCR Scan
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PDF
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100MHz-166M
256Kx32
100-pin
MG802C256
256Kx32
qfp 32 land pattern
qfp 64 0.4 mm pitch land pattern
maxim qfp marking
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