Untitled
Abstract: No abstract text available
Text: v3.2 SX Family FPGAs u e Leading Edge Performance • • • • Features 320 MHz Internal Performance 3.7 ns Clock-to-Out Pin-to-Pin 0.1 ns Input Setup 0.25 ns Clock Skew • • • • • • • • Specifications • • • • 12,000 to 48,000 System Gates
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THERMAL Fuse m20 tf 115 c
Abstract: SX v3.1 REQ64 A54SX08 A54SX16 A54SX32 PAR64 313 pin PBGA fq1200 THERMAL Fuse l20 tf 115 c
Text: v3.2 SX Family FPGAs u e Leading Edge Performance • • • • Features 320 MHz Internal Performance 3.7 ns Clock-to-Out Pin-to-Pin 0.1 ns Input Setup 0.25 ns Clock Skew • • • • • • • • Specifications • • • • 12,000 to 48,000 System Gates
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2032LV
Abstract: No abstract text available
Text: ispLSI and pLSI 2032V/LV ® 3.3V High Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — — — — — A IN • ispLSI OFFERS THE FOLLOWING ADDED FEATURES IM — 3.3V In-System Programmability Using Boundary
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032V/LV
2032LV
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LSC 132
Abstract: No abstract text available
Text: ispLSI and pLSI 3256A ® High Density Programmable Logic • HIGH-PERFORMANCE E CMOS TECHNOLOGY — fmax = 90 MHz Maximum Operating Frequency — tpd = 12 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable
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22B2 DIODE
Abstract: A54SX08A A54SX16A A54SX32A A54SX72A PQ208 TQ100 TQ144 TQ176
Text: v5.2 SX-A Family FPGAs u e Leading-Edge Performance • • • 250 MHz System Performance 350 MHz Internal Performance • • • Specifications • • • • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops
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22B2 DIODE
Abstract: RTSX-S datasheet SX FPGAs A54SX08A A54SX16A A54SX32A A54SX72A PQ208 TQ100 TQ144
Text: v5.1 SX-A Family FPGAs Leading-Edge Performance • • • 250 MHz System Performance 350 MHz Internal Performance • • • Specifications • • • • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops
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diode 2U 66
Abstract: No abstract text available
Text: v5.1 SX-A Family FPGAs Leading-Edge Performance • • • 250 MHz System Performance 350 MHz Internal Performance • • • Specifications • • • • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops
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sx08a
Abstract: No abstract text available
Text: v4.0 SX-A Family FPGAs u e Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5V PCI, 5V TTL, 3.3V LVTTL, 2.5V LVCMOS2 • 2.5V, 3.3V, and 5V Mixed-Voltage Operation with 5V Input Tolerance and 5V Drive Strength • Devices Support Multiple Temperature Grades
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A54SX16A
Abstract: No abstract text available
Text: v4.0 SX-A Family FPGAs u e Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5V PCI, 5V TTL, 3.3V LVTTL, 2.5V LVCMOS2 • 2.5V, 3.3V, and 5V Mixed-Voltage Operation with 5V Input Tolerance and 5V Drive Strength • Devices Support Multiple Temperature Grades
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22B2 DIODE
Abstract: Theta JC of FBGA A54SX08A A54SX16A A54SX32A A54SX72A PQ208 TQ100 TQ144 TQ176
Text: v5.3 SX-A Family FPGAs u e Leading-Edge Performance • • • 250 MHz System Performance 350 MHz Internal Performance • • • Specifications • • • • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops
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Untitled
Abstract: No abstract text available
Text: Preliminary GS890DV18D-330/300/250/200/167/133/100 9Mb Σ2x2B4V SigmaQuad SRAM 165-Bump BGA Commercial Temp Industrial Temp 100 MHz–330 MHz 2.5 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package
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GS890DV18D-330/300/250/200/167/133/100
165-Bump
165-bump,
144Mb
165-Pin
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k2333
Abstract: GS8342T GS8342T36
Text: Preliminary GS8342T08/18/36E-400/300/250/200/167 36Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–400 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus
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GS8342T08/18/36E-400/300/250/200/167
165-Bump
165-bump,
144Mb
GS834x36E-300T.
GS8342T
k2333
GS8342T
GS8342T36
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Untitled
Abstract: No abstract text available
Text: Preliminary GS81302S08/09/18/36E-333/300/250/200/167 144Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 4M x 36Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package
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GS81302S08/09/18/36E-333/300/250/200/167
165-Bump
36Features
165-bump,
144Mb
GS866x36E-300T.
81302Sxx
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Untitled
Abstract: No abstract text available
Text: Preliminary GS81302T19/37E-400/375 165-Bump BGA Commercial Temp Industrial Temp 144Mb SigmaCIO DDR-II+ Burst of 2 SRAM 400 MHz–375 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus
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GS81302T19/37E-400/375
165-Bump
165-bump,
144Mb
GS81302Tx36E-400T.
GS81302Txx
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GS8182S18BD-167
Abstract: GS8182S18BD-200 GS8182S18BD-250 GS8182S18BD-300
Text: Preliminary GS8182S08/09/18BD-333/300/250/200/167 18Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package
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GS8182S08/09/18BD-333/300/250/200/167
165-Bump
GS8182S08BGD-167I
GS818x36BD-300T.
GS8182S18BD-167
GS8182S18BD-200
GS8182S18BD-250
GS8182S18BD-300
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Untitled
Abstract: No abstract text available
Text: Preliminary GS81302S08/09/18/36E-333/300/250/200/167 144Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package
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GS81302S08/09/18/36E-333/300/250/200/167
144Mb
165-Bump
165-bump,
GS81302S08GE-200I
GS81302S08GE-167I
GS866x36E-300T.
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GS8182S18BD
Abstract: No abstract text available
Text: Preliminary GS8182S08/09/18BD-333/300/250/200/167 18Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package
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GS8182S08/09/18BD-333/300/250/200/167
165-Bump
144Mb
165-bump,
Ro82S08/09/18BD-333/300/250/200/167
GS8182S08GBD-167I
GS818x36BD-300T.
GS8182S18BD
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2032LV
Abstract: TMS3534
Text: ispLSI 2032V/LV 3.3V High Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — — — — — fmax = 100 MHz Maximum Operating Frequency tpd = 7.5 ns Propagation Delay A1 A2 D Q GLB A6 D Q D Q A5 D Q A3 A4
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032V/LV
0139Bisp/2000
2032LV
TMS3534
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Untitled
Abstract: No abstract text available
Text: Preliminary GS8182R08/18/36BD-333/300/250/200/167 18Mb SigmaCIO DDR-II Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus
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GS8182R08/18/36BD-333/300/250/200/167
165-Bump
GS818x36BD-300T.
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74AS1004
Abstract: SCYD001 XDS510 XDS510 MPSD 67996-114 ACT8990 74F175 74LVT240 ACT8999 SPDU079A
Text: JTAG/MPSD Emulation Technical Reference 1994 Printed in U.S.A., December 1994 2617709–9741 revision A SPDU079A JTAG/MPSD Emulation Technical Reference December 1994 SPDU079 Printed on Recycled Paper Running Title—Attribute Reference IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any
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SPDU079A
SPDU079
74AS1004
SCYD001
XDS510
XDS510 MPSD
67996-114
ACT8990
74F175
74LVT240
ACT8999
SPDU079A
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ACTEL flashpro datasheet
Abstract: INVERTER 10kW eX256 SCHEMATIC 10kw inverter RT54SX-S FLASHPRO LITE
Text: v2.0 eX Automotive Family FPGAs Specifications • • • • FuseLock • Design Support from Actel’s Designer Software and Libero Integrated Design Environment IDE • Up to 100% Resource Utilization with 100% Pin Locking • Deterministic Timing
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SPDU079A
Abstract: ACT8990 XDS510 MPSD 74AS1004 JTAG(MINI)14 pin 74F175 74LVT240 ACT8999 TL7705A XDS510
Text: JTAG/MPSD Emulation Technical Reference 1994 Printed in U.S.A., December 1994 2617709–9741 revision A SPDU079A JTAG/MPSD Emulation Technical Reference December 1994 SPDU079 Printed on Recycled Paper Running Title—Attribute Reference IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any
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SPDU079A
SPDU079
12-pin
14-pin
14-pin,
XDS510
SPDU079A
ACT8990
XDS510 MPSD
74AS1004
JTAG(MINI)14 pin
74F175
74LVT240
ACT8999
TL7705A
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GS8182R08GBD
Abstract: No abstract text available
Text: Preliminary GS8182R08/18/36BD-333/300/250/200/167 18Mb SigmaCIO DDR-II Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus
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GS8182R08/18/36BD-333/300/250/200/167
165-Bump
144Mb
165-bump,
GS818x36BD-300T.
GS8182R08GBD
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EX256-TQ100
Abstract: No abstract text available
Text: Revision 10 eX Family FPGAs Leading Edge Performance • 240 MHz System Performance • 350 MHz Internal Performance • 3.9 ns Clock-to-Out Pad-to-Pad Specifications • 3,000 to 12,000 Available System Gates • Maximum 512 Flip-Flops (Using CC Macros)
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