1,048 16 BIT Search Results

Contextual Info: DATA SHEET / MOS INTEGRATED CIRCUIT //PD42S16160L, 4216160L, 42S18160L, 4218160L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, FAST PAGE MODE, BYTE READ/WRITE MODE Description The ¿¡PD42S16160L, 4216160L, 42S18160L, 4218160Lare 1,048, 576 words by 16 bits CMOS dynamic RAMs.

uPD4216160L

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD42S16160L, 4216160L, 42S18160L, 4218160L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, FAST PAGE MODE, BYTE READ/WRITE MODE Description The µPD42S16160L, 4216160L, 42S18160L, 4218160L are 1,048, 576 words by 16 bits CMOS dynamic RAMs.

UPD42S18160G5-70-7-JF

Abstract: UPD42S18160G5707JF uPD42S18160-50 UPD4216160G uPD42S18160G5-50-7JF UPD4216160G5-50 PD42S18160-60 UPD42S18160G5-60-7JF NEC 4216160 UPD4218160G5-80-7JF
Contextual Info: DATA SHEET / MOS INTEGRATED CIRCUIT / PD42S16160,4216160,42S18160,4218160 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, FAST PAGE MODE, BYTE READ/WRITE MODE D e s c rip tio n The /xPD42S16160, 4216160, 42S18160, 4218160 are 1,048, 576 words by 16 bits CMOS dynamic RAMs. The

IC-3217

Abstract: PD42S18160 NEC 4216160 UPD4218160G5-50
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD42S16160, 4216160, 42S18160, 4218160 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, FAST PAGE MODE, BYTE READ/WRITE MODE Description The µPD42S16160, 4216160, 42S18160, 4218160 are 1,048, 576 words by 16 bits CMOS dynamic RAMs. The

4218160

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD42S18160L, 4218160L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, FAST PAGE MODE, BYTE READ/WRITE MODE Description The µPD42S18160L, 4218160L are 1,048, 576 words by 16 bits CMOS dynamic RAMs. The fast page mode and

Contextual Info: Preliminary information •■ AS4C1M 16F5 A 5V 1M x 16 C M O S DRAM fast page mode Features • 1024 refresh cycles, 16 m s refresh interval • O rganization: 1,048 ,5 7 6 w ords x 16 bits • H igh speed - KAS-only or CAS-before-KAS refresh • R ead-m odify-w rite

4218160LE-60

Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT ¿¿PD 42S18160, 4 2 1 8 1 6 0 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, FAST PAGE MODE, BYTE READ/WRITE MODE Description The ,uPD42S18160, 4218160 are 1,048, 576 words by 16 bits CMOS dynamic RAMs. The fast page mode and

4218160-60

Abstract: 4218160 IC-3217 4218160G5 UPD42S18160LE-60 PD42S18160
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD42S18160, 4218160 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, FAST PAGE MODE, BYTE READ/WRITE MODE Description The µ PD42S18160, 4218160 are 1,048, 576 words by 16 bits CMOS dynamic RAMs. The fast page mode and byte read/write mode capability realize high speed access and low power consumption.

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT ¿¿PD4 2 S 1 8 1 6 0 L , 4 2 1 8 1 6 0 L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, FAST PAGE MODE, BYTE READ/WRITE MODE The ,uPD42S18160L, 4218160L are 1,048, 576 words by 16 bits CMOS dynamic RAMs. The fast page mode and

Contextual Info: DATA SHEET / MOS INTEGRATED CIRCUIT ¿¿PD 42S16160,4216160,42S18160,4218160 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, FAST PAGE MODE, BYTE READ/WRITE MODE Description The ¿¡PD42S161 60 , 4 2 1 6 1 6 0 , 4 2 S 1 81 60 , 4 2 1 8 1 6 0 are 1,048, 5 7 6 words by 16 bits C M O S dynam ic RAM s. The

Contextual Info: Preliminary information •■ AS4C1M16F5 II 5V 1M x 16 C M O S DRAM fast page mode Features • O rganization: 1,048 ,5 7 6 w ords • H igh speed X • 1024 refresh cycles, 16 m s refresh interval 16 bits - K A S -o n ly o r C A S -b e fo r e -K A S r e f r e s h

1MX16

Abstract: AS4LC1M16S0 4lc2m8
Contextual Info: AS4LC2M8S0 AS4LC1M16S0 H igh Perform ance 2MX8/1MX16 CMOS DRAM 1 6 M egabit CM O S synchronous DRAM Advance information Features • Organization: 1,048 ,5 7 6 w ords x 8 bits x 2 banks 2M x8 52 4 ,2 8 8 w ords x 16 bits x 2 banks (lM x 16) • All signals referenced to positive edge o f dock

MSM51V18165A

Abstract: MSM51V18165
Contextual Info: O K I Semiconductor M SM 51V18165A_ 1,048,576-Ward x 16-Blt DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSM51V18165A is a 1,048¿76-w ord x 16-bit dynam ic RAM fabricated in O KI’s CM OS silicon gate technology. The M SM 51V18165A achieves high integration, high-speed operation, and lowpower consumption due to quadruple polysilicon double metal CM OS. The M SM 51V18165A is

MSM538002C

Abstract: SM535
Contextual Info: O K I Semiconductor MSM538002C r 524,288-Word x 16-Bit or 1,048,576-Word x 8-Bit Mask ROM ~~ ~ D E S C R IP TIO N The OKI MSM538002C is a high-speed CMOS Mask ROM that can electrically switch between 524 288word x 16-bit and 1,048 576-word x 8-bit configurations. The MSM538002C operates o n X * 5 0 V

IC-321B

Abstract: p421e P421E-400A
Contextual Info: DATA SHEET / MOS INTEGRATED CIRCUIT jUPD42S16160L, 4216160L, 42S18160L, 4218160L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, FAST PAGE MODE, BYTE READ/WRITE MODE Description T h e ^ P D 4 2 S 1 6 1 6 0 L , 4216160L, 42S 18 1 6 0 L , 4 2 1 8 1 6 0 L are 1,048, 576 w ords by 16 bits C M O S dyna m ic RAMs.

MSM538022C

Contextual Info: O K I Semiconductor MSM538022C 524,288-W ord x 16-B it o r 1,048,576-W ord x 8 -Bit M ask ROM DESCRIPTION The OKI MSM538022C is a high-speed CMOS M ask ROM th at can electrically sw itch betw een 524 288w o rd x 16-bit a n d 1,048 576-w ord x 8-bit configurations. The MSM538022C o perates o n T s in i 5 0 V

D42S18160

Abstract: d42s181 D42S1816 UPD42S18160LG5A-60
Contextual Info: D A T A SHEET / MOS INTEGRATED CIRCUIT /¿ P D 4 2 S 1 6 1 6 0 L , 4 2 1 6 1 6 0 L. 4 2 S 1 8 1 6 0 L , 4 2 1 8 1 6 0 L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, FAST PAGE MODE, BYTE READ/WRITE MODE Description The /¿PD42S16160L, 4216160L, 4 2S 18160L, 4 2 18160L are 1,048, 576 w ords by 16 bits CMOS dynam ic RAMs.

NEC 4216160

Contextual Info: DATA SHEET NEC / MOS INTEGRATED CIRCUIT _ _ _ _ _ _ _ /¡¿ P D 42S 16160, 4216160, 42S 18160,4218160 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, FAST PAGE MODE, BYTE READ/WRITE MODE Description T h e /1 P D 4 2 S 1 6 1 6 0 ,4 21 6160, 4 2 S 1 8 1 6 0 ,4 2 1 8 1 6 0 a re 1,048, 576 w o rds by 16 b its C M O S d y n a m ic RA M s. T he

EZ 929

Abstract: S1616
Contextual Info: DATA SHEET NEC / MOS INTEGRATED CIRCUIT _ _ _ _ _ _ _ _ //¿PD42S16160L, 4216160L, 42S18160L, 4218160L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 1 M-W ORD B Y 16-BIT, FA ST P A G E M ODE, B Y T E READ/WRITE M O D E D escrip tion T h e ¿ iP D 4 2 S 1 6 1 6 0 L , 4 2 1 6 1 6 0 L , 4 2 S 1 6 1 6 0 L , 4 2 1 8 1 6 0 L a re 1,048, 576 w ord s by 16 b its C M O S d y n a m ic R A M s .

A112-4D

Contextual Info: COUL D I N C / G O U L D A M I 40E D • nnuLD MQSS'ilb 0013233 1 ■ A M I 8M Bit 1 048,576 x 8) . Static CMOS Mash ROM Preliminary Data Sheet A i f l i M * Semiconductors S638000(INI x 8) 1 iS ftH v Y > Features General Description • Fast Access Time:

LH538000

Abstract: 538000-1B
Contextual Info: LH538000 FEATURES • CMOS 8M 1M x 8 / 512K x 16 Mask-Programmabie ROM DESCRIPTION 1,048,576 x 8 bit organization (Byte mode) 524,288 x 16 bit organization (Word mode) • BYTE input pin selects bit configuration • Access time: 200 ns (MAX.) • Power consumption:

Contextual Info: Mar 25, 1991 M5M51014J-25t-35,-45 MITSUBISHI 1.Q4&376BITÇ262144-WORD BY 4-BIT STATIC RAM DESCRIPTION The M5M51014 is a family of262,144word by 4-bit static RAMs, fabricated with the high performance CMOS silicon gate process and designed for high-speed application. These

modbus-rtu

Abstract: LCM200 solid state variable relay Weight controller BLH weight 1045 FISHER
Contextual Info: Model LCm-200 Vishay BLH Transducers Weight Controller FEATURES • Designed for NIST Handbook 44 compliance • Canadian weights and measures and NTEP CoC • Rate-by-weight Mass Flow operation • Expansion slot for A-B remote I/O, Modbus Plus, or future

Contextual Info: TOSHIBA TC 551001 BPI/BFI/BFTI/BTRI/BSTI/BSRI-85,-10 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 131,072-WORD BY 8-BIT STATIC RAM DESCRIPTION The TC551001BPI/BFI/BFTI/BTRI/BSTI/BSRI is a 1,048 576-bit static random access memory SRAM organized as 131,072 words by 8 bits. Fabricated using Toshiba’s CMOS Silicon gate process technology, this