AT91SAM3U4
Abstract: at91sam3 1N1308 MAR 735 REGULATOR IC 7912 pin identify AT91SAM3U4E SAM3u1 AT91SAM3U 3961 G.E 0x20180
Text: Features • Core • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 96 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set Memories – From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator,
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128-bit
6430F
21-Feb-12
AT91SAM3U4
at91sam3
1N1308
MAR 735
REGULATOR IC 7912 pin identify
AT91SAM3U4E
SAM3u1
AT91SAM3U
3961 G.E
0x20180
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ARM926T
Abstract: ic str 6454 s11 stopping compound motorola 7824 BT OSC26M CNC DRIVES ptc temperature sensor 400c 4*4 matrix keypad 17521 rca SAMSUNG NAND FLASH K9F5608
Text: i.MX21 Applications Processor Reference Manual Document Number: MC9328MX21RM Rev. 3 04/2007 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370
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MC9328MX21RM
CH370
ARM926T
ic str 6454
s11 stopping compound
motorola 7824 BT
OSC26M
CNC DRIVES
ptc temperature sensor 400c
4*4 matrix keypad
17521 rca
SAMSUNG NAND FLASH K9F5608
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AN2946
Abstract: MSC7110 MSC7112 MSC7116 SC1400 modulo
Text: Freescale Semiconductor Application Note AN2946 Rev. 0, 2/2005 MSC711x Time-Division Multiplexing TDM Usage Examples By Barbara Johnson The time-division multiplexing (TDM) interface on the Freescale MSC711x devices provides full duplex, bidirectional communication over a single bus. This application note presents
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AN2946
MSC711x
MSC711r
AN2946
MSC7110
MSC7112
MSC7116
SC1400
modulo
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GCM 38112
Abstract: Wifi to I2C ST ATUC3A4256S AT32UC3A3 dsp ssb modulation demodulation barcode reader using avr AT32UC3A64 ATUC3A3256 DesignWare Hi-Speed USB On-The-Go Controller AT32UC3A3256S
Text: Features • High Performance, Low Power 32-bit AVR Microcontroller • • • • • • • • • • • • – Compact Single-Cycle RISC Instruction Set Including DSP Instruction Set – Read-Modify-Write Instructions and Atomic Bit Manipulation
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32-bit
51DMIPS/MHz
92DMIPS
66MHz
36MHz
256KBytes,
128KBytes,
64KBytes
32072D04/2011
GCM 38112
Wifi to I2C ST
ATUC3A4256S
AT32UC3A3
dsp ssb modulation demodulation
barcode reader using avr
AT32UC3A64
ATUC3A3256
DesignWare Hi-Speed USB On-The-Go Controller
AT32UC3A3256S
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FTL3-2
Abstract: 8 bit modified booth multipliers S3C3410X 0xc01c IRM bed
Text: 22-S3-C3410X-062001 USER'S MANUAL S3C3410X 16-Bit CMOS Microcontrollers Revision 2 NOTIFICATION OF REVISIONS ORIGINATOR: Samsung Electronics, SOC Development Group, Ki-Heung, South Korea PRODUCT NAME: S3C3410X RISC Microcontroller DOCUMENT NAME: S3C3410X User's Manual, Revision 2
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22-S3-C3410X-062001
S3C3410X
16-Bit
S3C3410X
22-S3-C3410X-06-2001
FTL3-2
8 bit modified booth multipliers
0xc01c
IRM bed
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s3c46
Abstract: S3C4510B S3C4510 SDLC 8044 Transistor TEO 1279 diagram TCON resistor 270 ohm ARM7 Series 38109 0x303C
Text: S3C4510B 1 PRODUCT OVERVIEW PRODUCT OVERVIEW OVERVIEW Samsung's S3C4510B 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller solution for Ethernet-based systems. An integrated Ethernet controller, the S3C4510B, is designed for use in
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S3C4510B
S3C4510B
16/32-bit
S3C4510B,
208-pin
s3c46
S3C4510
SDLC 8044
Transistor TEO 1279
diagram TCON
resistor 270 ohm
ARM7 Series
38109
0x303C
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dSMC
Abstract: WinChip-2 Phoenix BIOS manual f.34 cyrix Cyrix 6x86mx AK-02 diode T35 12H P54C P55C TR12
Text: Preliminary Information PROCESSOR Data Sheet Preliminary Information April 1999 IDT WINCHIPTM 3 PROCESSOR DATA SHEET This is Version 0.9 of the IDT WinChip 3 Processor data sheet. The latest versions of this data sheet may be obtained from www.winchip.com
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LH75401
Abstract: LH75401N0Q100C0 LH75411 LH75411N0Q100C0 LQFP144
Text: LH75401/LH75411 System-on-Chip Preliminary data sheet DESCRIPTION • JTAG Debug Interface and Boundary Scan The NXP BlueStreak LH75401/LH75411 family consists of two low-cost 16/32-bit System-on-Chip SoC devices. • Single 3.3 V Supply • LH75401 — contains the superset of features.
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LH75401/LH75411
LH75401/LH75411
16/32-bit
LH75401
144-pin
LH75411
LH75401,
LH75401
12-bit
12-bit
LH75401N0Q100C0
LH75411N0Q100C0
LQFP144
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R4000
Abstract: R4640 R4650 R4700 R5000 RM5230TM R5000 mips MIPS RM5230
Text: RM5230 Superscalar Microprocessor with 32-Bit System Bus FEATURES • Dual Issue superscalar microprocessor — 100, 133, 150 and 175 MHz operating frequencies — 210 Dhrystone2.1 MIPS — SPECInt95 3.5, SPECfp95 3.7 • System interface optimized for embedded applications
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RM5230TM
32-Bit
SPECInt95
SPECfp95
RM5230-DS0011409910
R4000
R4640
R4650
R4700
R5000
R5000 mips
MIPS RM5230
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VFP9-S
Abstract: CP15 ARM Architecture Reference Manual VFP9S 0x00000000b
Text: VFP9-S Vector Floating-point Coprocessor r0p2 Technical Reference Manual Copyright 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0238B VFP9-S r0p2 Vector Floating-point Coprocessor Technical Reference Manual Copyright © 2002, 2003 ARM Limited. All rights reserved.
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0238B
VFP9-S
CP15
ARM Architecture Reference Manual
VFP9S
0x00000000b
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Untitled
Abstract: No abstract text available
Text: Standard Products ACT 7000ASC 64-Bit Superscaler Microprocessor January 24, 2005 FEATURES • ■ Full militarized PMC-Sierra RM7000A microprocessor Dual Issue symmetric superscalar microprocessor with instruction prefetch optimized for system level price/performance
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7000ASC
64-Bit
RM7000A
RM52xx
SCD7000
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0x1000000
Abstract: RF cmos LNA ATSAM3S8CA-AU CI 4046 RS232 Wireless Bluetooth Transceiver 0x4143 ATSAM3S l 7135 SD812 DSAASSA000857.
Text: Features • Core • • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 64 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set Pin-to-pin compatible with AT91SAM7S legacy products (64-pin versions), SAM3S4/2/1 products
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AT91SAM7S
64-pin
128-bit
1090A
10-Feb-12
0x1000000
RF cmos LNA
ATSAM3S8CA-AU
CI 4046
RS232 Wireless Bluetooth Transceiver
0x4143
ATSAM3S
l 7135
SD812
DSAASSA000857.
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ADS1602
Abstract: AK4550 AN3067 DAC8830 SC1400
Text: Document Number: AN3067 Rev. 1, 02/2008 Interfacing the MSC711x TDM to A/D, D/A and Codecs by Barbara Johnson Digital Systems Division Freescale Semiconductor, Inc. Austin, TX The time-division multiplexing TDM interface is a full-duplex serial port that allows MSC711x DSPs to
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AN3067
MSC711x
MSC711X
ADS1602
AK4550
AN3067
DAC8830
SC1400
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24c16 eeprom resetting only circuit diagram and d
Abstract: a180, transformer atmel 24c16 SAA7322 intel core i3 MOTHERBOARD CIRCUIT diagram mba mini projects SB82371SB TriMedia TM-1000 ATMEL 220 24C16 trimedia tm1300
Text: INTEGRATED CIRCUITS TM-1300 Media Processor Product Specification Supersedes data of 2000 May 30 File under INTEGRATED CIRCUITS, TR1 2000 Sep 30 Terms and Conditions TERMS AND CONDITIONS Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes,
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TM-1300
24c16 eeprom resetting only circuit diagram and d
a180, transformer
atmel 24c16
SAA7322
intel core i3 MOTHERBOARD CIRCUIT diagram
mba mini projects
SB82371SB
TriMedia TM-1000
ATMEL 220 24C16
trimedia tm1300
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RC64475
Abstract: No abstract text available
Text: ◆ Implements MIPS-III Instruction Set Architecture ISA 3.3V I/O ◆ Software compatible with entire RISController Series of Embedded Microprocessors
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RC64474
RC4640
RC64475
RC4650
128-pin
32-bit
208-pin
64-bit
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an-608 national
Abstract: AN-608 C1995 NS32GX32
Text: INTRODUCTION The NS32GX32 provides two on-chip caches A 512-byte Instruction Cache IC and a 1024-byte Data Cache These caches are blocks of very fast local memory that hold copies of instructions and data most frequently used by the CPU For most general purpose applications spatial and
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NS32GX32
512-byte
1024-byte
20-3A
an-608 national
AN-608
C1995
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RM5261
Abstract: R4000 R4650 R5000 RM5200 RM5231
Text: RM5261 Microprocessor with 64-Bit System Bus Data Sheet Released RM5261 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet Proprietary and Confidential Issue 1, March 2001 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
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RM5261TM
64-Bit
RM5261
64-Bit
PMC-2002241,
PMC-2002241
RM5261
R4000
R4650
R5000
RM5200
RM5231
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R4000
Abstract: RM5200 RM5261A
Text: RM5261A Microprocessor with 64-Bit System Bus Data Sheet Preliminary RM5261A™ RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet Proprietary and Confidential Preliminary Issue 1, March 2001 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
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RM5261ATM
64-Bit
RM5261ATM
64-Bit
PMC-2002240,
PMC-2002240
SysAD45
R4000
RM5200
RM5261A
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SPARTAN-3e microblaze
Abstract: DS452 vhdl code for bram lmb bus timing
Text: LMB BRAM Interface Controller v2.10b DS452 April 24, 2009 Product Specification Introduction LogiCORE Facts This document provides the design specification for the Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller. The LMB BRAM Interface Controller connects to an
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DS452
SPARTAN-3e microblaze
vhdl code for bram
lmb bus timing
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R4000
Abstract: RM5200 RM5261A
Text: RM5261A Microprocessor with 64-Bit System Bus Data Sheet Preliminary RM5261A™ RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet Proprietary and Confidential Preliminary Issue 2, September 2001 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
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RM5261ATM
64-Bit
RM5261ATM
64-Bit
PMC-2002240,
PMC-2002240
SysAD45
R4000
RM5200
RM5261A
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tag a2
Abstract: ARGB888 CY7C68013A ITU656 RGB565 RGB888 ECP2-50 RGB-16 802.3 CRC32
Text: LCD-Pro IP user manual UM0011 v1.0 – 14 July 2009 User Manual: Overview This document describes the LCD-Pro IP architecture, including the next cores: UltiEVC display controller, UltiEBB 2D graphic accelerator, UltiEMC DDR memory controller, UltiVidin video input core, UltiDMA DMA controller, UltiSPI2AHB SPI
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UM0011
DS0031)
tag a2
ARGB888
CY7C68013A
ITU656
RGB565
RGB888
ECP2-50
RGB-16
802.3 CRC32
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qed rm5200
Abstract: No abstract text available
Text: RM5271 Microprocessor with External Cache Interface Document Rev. 1.3 Date: 02/2000 FEATURES • High-performance floating point unit - up to 700 MFLOPS — Single cycle repeat rate for common single precision operations and some double precision operations
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RM5271TM
64-bitmultiplexed
125MHz
RM5271-DS0012000001
RM5271
qed rm5200
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ARM7500FE
Abstract: 08FF 0x032000F8
Text: 1 18 11 I/O Subsystems This chapter describes the ARM7500FE I/O subsystems. 18.1 Introduction 18-2 18.2 I/O Address Space Usage 18-3 18.3 Additional I/O Chip Select Decode Logic 18-4 18.4 Simple 8MHz I/O 18-4 18.5 Module I/O 18-11 18.6 PC Bus-style I/O 18-15
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ARM7500FE
0077B
IOCK32
32MHz.
08FF
0x032000F8
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Untitled
Abstract: No abstract text available
Text: The ARM Processor Family This Data Sheet is one of a series describing the ARM Family of products from GEC Plessey Semiconductors. The table below shows the current range of 32-bit RISC M icroprocessors/M icrocontrollers. GPS Name P ackag e Description 32 bit RISC core with 32 bit address range.
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32-bit
100PQFP
144TQFP
160PQFP
ser26
FIQ26
1RQ26
upervisor26.
37bfl522
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