07H06H Search Results

A17-A14

Contextual Info: W89C940 yfTTPX S S S S S S S S S S S S S S S S S S S S S S S S S S \\\\\\ E ¡ecirosri ic s C o rp . ELANC-PCI TWISTED-PAIR ETHER-LAN CONTROLLER WITH

Contextual Info: Preliminary Information AMD-640 TM System Controller Data Sheet AM DËI Preliminary Information 1997 Advanced Micro Devices, Inc. A ll rights reserved. A dvanced M icro D evices, Inc. "AM D" reserves the right to m ake changes in its products w ithout n otice in order to im prove design or perform ance characteristics.

82C556M

Abstract: OCH168 82C557M 82C558 OPTi 82C546 82c556 CI VIPER 17H 82C558M opti 82c556 IBM motherboard schematics
Contextual Info: twain 82C556M/82C557M/82C558M Viper-M Multimedia Chipset Preliminary Data Book Revision: 1.0 912-2000-010 April 1995 • RODm ^b □ Powered by ICminer.com Electronic-Library Service CopyRight 2003 038 Copyright Copyright 1995, OPTi Inc. All rights reserved. No part of this publication may be reproduced, transmitted, transcribed, stored

sekisui 5760

Abstract: sis950 SiS chipset 486 SEAGATE st51080n Bt848KPF KSV884T4A1A-07 lad1 5vdc SiS chipset SiS301 kingmax usb flash drive
Contextual Info: SiS540 Super 7 2D/3D Ultra-AGPTM Single Chipset Content Figure .vi Table. vii

8237 DMAC

Abstract: 8237 DMA Controller Intel 8237 dma controller DMA Controller 8237 Intel 8237 8237 7 independent DMA channels Base Station subsystem I/O FUNCTION IN DESKTOP MOTHERBOARD Intel 8237 dma interrupt driven i/o in intel
Contextual Info: Implementing Legacy Audio on the PCI Bus Revision 1.2 Written by Gary Solomon Sr. Staff Engineer Platform Architecture Lab gary_solomon@ccm.jf.intel.com Intel Corporation Information in this document is provided in connection with Intel products. No license, express or

AMD K6

Contextual Info: Preliminary Information AMD-645 Peripheral Bus Controller Data Sheet AMDËI Preliminary Information 1997 Advanced M icro Devices, Inc. A ll rig h ts re se rv e d . A d v a n c e d M icro D evices, Inc. "A M D " re s e rv e s th e r ig h t to m a k e c h a n g e s in its

Contextual Info: HOLTEK H r HT80229 Ethernet Controller with Built-in RAM Features • • • • • • Single 5V Power Supply Built-in pre-fetch function for rem ote DMA Built-in pre-equalization circuit Built-in SRAM Provides both AUI and 10 BASE-T interface Provides auto-detection between 10BASE-T

4116 DRAM 16Kx1

Abstract: 82C206 82C558
Contextual Info: 82C556/82C557/82C558 Figure 2-3 82C557 SYSC Block Diagram I R ES ET PW RG D CLK ECLK LCLK HA[31:3] BE[7:0]# M /IO # D/C# W /R # /IN V /D IR TYO AD S # BRDY# NA# KEN #/LM EM # EADS#/(W B/W T#) HITM # CACHE# SM IACT# EC D OE# O C D O E# ECAWE#/CACSOO# OCAW E#/CACS1 O#

e/15-16M

Contextual Info: Preliminary Information AMDÌ1 A M D - 751" System Controller Data Sheet Publication #21910 Rev:D Issue Date: August 1999 H D25 752 5 OObaOBt. b l S 1999 Advanced Micro Devices, Inc. A ll rights reserved. T he c o n te n ts of th is d o cu m en t a re p ro v id ed in co n n ectio n w ith A d v an ced

ht93c46

Abstract: HT80232 93C46 SOCKET coupling transformer ethernet tp-link 10MHZ NE2000 MAR6
Contextual Info: HT80232 Ethernet Controller/PCI ECON-PCI Features • • • • • • • Single chip Ethernet controller for PCI bus interface Register compatible with NE2000 External 15ns access time SRAM for data transfer Integrated 10BaseT TP interface – Smart squelch circuit with programmable

8237 DMA Controller

Abstract: MPU401 MPU-401 sound blaster programming PCI BUS
Contextual Info: Implementing Legacy Audio on the PCI Bus Revision 2.1 Written by Gary Solomon Sr. Staff Engineer Platform Architecture Lab gary_solomon@ccm.jf.intel.com Intel Corporation Information in this document is provided in connection with Intel products. No license, express or implied,

GAMEport CONTROLLER

Abstract: 8237 DMA Controller Base Station subsystem Intel 8237 dma MIDI mpu-401 interface usb gameport adapter MPU401 MPU-401 907FH 8237 DMAC
Contextual Info: Implementing Legacy Audio on the PCI Bus Revision 2.1a Written by Gary Solomon Senior Systems Architect Platform Architecture Lab gary_solomon@ccm.jf.intel.com Intel Corporation Information in this document is provided in connection with Intel products. No license, express or implied,

Contextual Info: User’s Manual, V1.2, Feb. 2003 TC11IB Peripheral Units 32-Bit Single-Chip Microcontroller Microcontrollers N e v e r s t o p t h i n k i n g . Edition 2003-02 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany Infineon Technologies AG 2003.

Contextual Info: User’s M anual, V1.1, Apr. 2002 TC11IB P e ri p h e ra l U n i t s 3 2 -B i t S i n g l e - C h i p M ic r o co n t ro l l e r M i c r o c o n t ro l le r s N e v e r s t o p t h i n k i n g . Edition 2002-04 Published by Infineon Technologies AG, St.-Martin-Strasse 53,

HT80229

Abstract: 12th open MAR3 MAR4 ne2000 PIN assignments of UTP cables 10MHZ MA13
Contextual Info: HT80229 Ethernet Controller with Built-in RAM Features • • • • • • • • • • Single 5V Power Supply Built-in pre-fetch function for remote DMA Built-in pre-equalization circuit Built-in SRAM Provides both AUI and 10 BASE-T interface Provides auto-detection between 10BASE-T

10MHZ

Abstract: HT80232 NE2000 HT93C46
Contextual Info: HT80232 Preliminary Ethernet Controller/PCI ECON-PCI Features • • • • • • Single chip Ethernet controller for PCI bus interface Register compatible with NE2000 External 15ns access time SRAM for data transfer Integrated 10BaseT TP interface – Smart squelch circuit with programmable

CH365P

Abstract: CH365 8255 RAM 24C0X CH421 8255 ISA 9502h sram62256 24c02 mcu 8255 pci
Contextual Info: １ CH365 中文手册（一） PCI 总线接口芯片 CH365 中文手册 版本：1C http://wch.cn 1概述 CH365 是一个连接 PCI 总线的通用接口芯片，支持 I/O 端口映射、存储器映射、扩展 ROM 以及中 断。CH365 将 32 位高速 PCI 总线转换为简便易用的类似于 ISA 总线的 8 位主动并行接口，用于制作

ht93c46

Abstract: HT80232 MA10 MA11 MA12 MA13 NE2000
Contextual Info: HOLTEK r r HT80232 Ethernet Controller/PCI ECON-PCI Features • • • • • • Single chip Ethernet controller for PCI bus interface Register compatible with NE2000 External 15ns access time SRAM for data transfer Integrated lOBaseT TP interface - Sm art squelch circuit with programmable