XR20V2172IL64
Abstract: XR20V2172IL64-F
Text: XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER JULY 2008 REV. 1.0.1 GENERAL DESCRIPTION FEATURES The XR20V21721 V2172 is a high performance two channel universal asynchronous receiver and transmitter (UART) with 64 byte TX and RX FIFOs, a
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XR20V2172
64-BYTE
RS232
XR20V21721
V2172)
V2172
RS-232
01-Aug-09
XR20V2172IL64
XR20V2172IL64-F
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Untitled
Abstract: No abstract text available
Text: XRT8001 WAN Clock for T1 and E1 Systems October 2001-1 GENERAL DESCRIPTION • Generates Output Clock Frequencies Ranging The XRT8001 WAN Clock is a dual-phase-locked loop chip that generates two very low jitter output clock signals that can be used for synchronization clocks in
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XRT8001
XRT8001
56kHz,
64kHz
54MHz
048MHz
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Untitled
Abstract: No abstract text available
Text: XRT73L02M xr TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT MAY 2003 GENERAL DESCRIPTION The XRT73L02M is a two-channel fully integrated Line Interface Unit LIU for E3/DS3/STS-1 applications. It incorporates independent Receivers, Transmitters in a single 100 pin TQFP package.
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XRT73L02M
XRT73L02M
XRT73L02MIV-F
TQFP100
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30186
Abstract: No abstract text available
Text: XRT8010 312MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS NOVEMBER 2003 REV. 1.0.2 DESCRIPTION • FEATURES The XRT8010 is a monolithic analog phase locked loop that provides a high frequency LVDS clock output, using a low frequency crystal or reference
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XRT8010
312MHZ
XRT8010
01-Aug-09
-350MHz
XRT8010IL-F
QFN16
30186
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Untitled
Abstract: No abstract text available
Text: XR19L202 TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER JULY 2007 REV. 1.0.1 GENERAL DESCRIPTION APPLICATIONS The XR19L202 L202 is a highly integrated device that combines a full-featured two channel Universal Asynchronous Receiver and Transmitter (UART) and RS232 transceivers. The L202 is designed to operate with a
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XR19L202
RS-232
RS232
EIA/TIA-232-F
/-15V
/-15kV
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N0044
Abstract: divide by 60 XRS10L240
Text: EXSTOR XRS10L140 SERIAL ATA II: PORT MULTIPLIER JANUARY 2009 REV. 1.05 test and loopback features is achieved in a low cost and lower power implementation. FEATURES GENERAL FEATURES • Five independent 3/1.5Gbps SATA ports. • Connects 1 host port to 4 device ports.
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XRS10L140
XRS10L140
01-Aug-09
N0044
divide by 60
XRS10L240
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RS-232 IBIS models
Abstract: 64-QFN XR19L222IL64F XR19L222IL64
Text: XR19L222 TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER JULY 2007 REV. 1.0.1 GENERAL DESCRIPTION APPLICATIONS The XR19L222 L222 is a highly integrated device that combines a full-featured two channel Universal Asynchronous Receiver and Transmitter (UART) and RS232 transceivers. The L222 is designed to operate with a
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XR19L222
RS-232
RS232
EIA/TIA-232-F
/-15V
/-15kV
RS-232 IBIS models
64-QFN
XR19L222IL64F
XR19L222IL64
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relay finder t29
Abstract: T74 relay finder t29 PLL 2400 MHZ
Text: XRT8000 -WAN Clock Synchronizer/Adapter for Communications HomeNewsCareers Investor Relations Contact Us PartnerNet Login Search CommunicationsInterfacePower Management XRT8000 Support Info Request How to Order Samples How to Buy Print this page WAN Clock Synchronizer/Adapter for Communications
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XRT8000
768kHz
150Hz
048kHz
relay finder t29
T74 relay
finder t29
PLL 2400 MHZ
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Untitled
Abstract: No abstract text available
Text: XRT59L91 Single-Chip E1 Line Interface Unit October 1999-1 FEATURES l Complete E1 CEPT line interface unit (Transmitter and Receiver) l Supports both Local- and Remote-Loop back Operations l Generates transmit output pulses that are compliant with the ITU-T G.703 Pulse Template
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XRT59L91
048Mbps
XRT59L91ID
16-lead
XRT5997IV
100-pin
XRT59L91ID-F
SOIC16
01-Aug-09
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Untitled
Abstract: No abstract text available
Text: XR16V794 -High Performance 2.25V to 3.6V Quad UART with Fractional Baud Rate HomeNewsCareers Investor Relations Contact Us PartnerNet Login Search CommunicationsInterfacePower Management XR16V794 Support Info Request Print this page High Performance 2.25V to 3.6V Quad UART with Fractional
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XR16V794
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MDIO communication protocol
Abstract: ibis sata MDC 1200 N0021 XRS10L120
Text: EXSTOR XRS10L120 SERIAL ATA II: PORT MULTIPLIER JUNE 2009 REV. 1.06 test and loopback features is achieved in a low cost and lower power implementation. FEATURES GENERAL FEATURES • Three independent 3/1.5Gbps SATA ports. • Connects 1 host port to 2 device ports.
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XRS10L120
XRS10L120
01-Aug-09
MDIO communication protocol
ibis sata
MDC 1200
N0021
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Untitled
Abstract: No abstract text available
Text: áç XRT71D00 E3/DS3/STS-1 JITTER ATTENUATOR SEPTEMBER 2001 REV. 1.2.0 GENERAL DESCRIPTION The XRT71D00 is a single channel, single chip Jitter Attenuator, that meets the Jitter transfer characteristic requirements specified in the ETSI TBR-24, Bellcore GR-499-CORE and GR-253-CORE standards.
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XRT71D00
XRT71D00
TBR-24,
GR-499-CORE
GR-253-CORE
GR499-CORE
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2 pin ir receiver
Abstract: No abstract text available
Text: XR19L212 TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER JULY 2007 REV. 1.0.1 GENERAL DESCRIPTION APPLICATIONS • Battery-Powered Equipment • Handheld and Mobile Devices • Handheld Terminals • Industrial Peripheral Interfaces • Point-of-Sale POS Systems
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XR19L212
RS-232
RS232
EIA/TIA-232-F
/-15V
/-15kV
2 pin ir receiver
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14411 baud rate generator
Abstract: XR16L2750
Text: XR16V2750 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO SEPTEMBER 2007 REV. 1.0.3 GENERAL DESCRIPTION The XR16V27501 V2750 is a high performance dual universal asynchronous receiver and transmitter (UART) with 64 byte TX and RX FIFOs. The device operates from 2.25 to 3.6 volts with 5 Volt tolerant
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XR16V2750
64-BYTE
XR16V27501
V2750)
ST16C2550
XR16L2750.
V2750
XR16L2750
XR16C2850
14411 baud rate generator
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Ox086
Abstract: 552 93c46
Text: XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT JULY 2008 REV. 1.0.1 GENERAL DESCRIPTION The XR17V2541 V254 is a single chip 4-channel 66MHz PCI (Peripheral Component Interconnect) UART (Universal Asynchronous Receiver and Transmitter) solution,
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XR17V254
66MHZ
XR17V2541
32-bit
33MHz
144-pin
01-Aug-09
Ox086
552 93c46
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Untitled
Abstract: No abstract text available
Text: XR-T3588/89 .the analog plus V.35 Interface Receiver/Transmitter company TM June 1997-3 FEATURES APPLICATIONS D Compatible with ITU-T V.35 and Bell 306 Interface Requirements D High Speed Data Transmission Systems D TTL Input Compatibility D Short Haul Modems
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XR-T3588/89
10Mbps)
01-Aug-09
XRT3588
XRT3588CP-F
PDIP18
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Relay NAIS Ds
Abstract: E3252 SG 2368 ATA 2388 ic 393 NAIS tf relay tes 5-2422
Text: áç XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER OCTOBER 2003 REV. 1.2.1 GENERAL DESCRIPTION The XRT72L50, single Channel DS3/E3 Framer IC is designed to accept user data from the Terminal Equipment and insert this data into the payload bitfields within an outbound DS3/E3 Data Stream. Further, the Framer IC is also designed to receive an inbound DS3/E3 Data Stream from the Remote Terminal Equipment and extract out the user data.
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XRT72L50
XRT72L50,
XRT72L50
DS3-M13,
XRT72L50IQ-F
PQFP100
01-Aug-09
Relay NAIS Ds
E3252
SG 2368
ATA 2388
ic 393
NAIS tf relay
tes 5-2422
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24444
Abstract: XRT5683AID-F XRT5683AIDf XRT5683AID
Text: XR-T5683A .the analog plus PCM Line Interface Chip company TM June 1997-3 FEATURES D TTL Compatible Interface D Single 5V Supply D Device Can Be Used as a Line Interface Unit Without Clock Recovery D Receiver Input Can Be Either Balanced or Unbalanced APPLICATIONS
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XR-T5683A
448Mbps
XR-T5683A
448Mbps,
XRT5683AIP-F
PDIP18
XRT5683AID-F
SOIC18
01-Aug-09
XRT5683A
24444
XRT5683AIDf
XRT5683AID
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relay finder t29
Abstract: No abstract text available
Text: áç XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR SEPTEMBER 2001 REV. 1.2.0 GENERAL DESCRIPTION The XRT71D03 is a three channel, single chip Jitter Attenuator, that meets the Jitter transfer characteristics requirements specified in the ETSI TBR-24, Bellcore GR-499 and GR-253 standards.
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XRT71D03
XRT71D03
TBR-24,
GR-499
GR-253
GR-235-CORE,
GR499-CORE
relay finder t29
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AM 770 DENSITY TRANSMITTER
Abstract: wandel goltermann RFZ wandel goltermann sna-2
Text: XRT5894 Four-Channel E1 Line Interface 3.3V or 5.0V March 2000-3 FEATURES D Compliant with ITU G.703 Pulse Mask Template for 2.048Mbps (E1) Rates D Four Independent CEPT Transceivers D Logical Inputs Accept either 3.3V or 5.0V Levels D Ultra-Low Power Dissipation
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XRT5894
048Mbps
XRT5894
01-Aug-09
XRT5894IV-F
TQFP64
AM 770 DENSITY TRANSMITTER
wandel goltermann RFZ
wandel goltermann sna-2
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SC16C752B
Abstract: No abstract text available
Text: XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO JUNE 2009 REV. 1.1.1 GENERAL DESCRIPTION The XR16M752/XR68M7521 M752 is a high performance dual universal asynchronous receiver and transmitter (UART) with 64 byte TX and RX FIFOs. The M752 operates from 1.62 to 3.63 volts. It
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XR16M752/XR68M752
64-BYTE
XR16M752/XR68M7521
TL16C752B
SC16C752B,
RS-485
XR68M752
01-Aug-09
SC16C752B
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M1172
Abstract: 1152 si dlm QFN32 pad xr20m1172il32-f
Text: XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO JUNE 2009 REV. 1.0.1 GENERAL DESCRIPTION FEATURES The XR20M11721 M1172 is a high performance two channel universal asynchronous receiver and transmitter (UART) with 64 byte TX and RX FIFOs and a selectable I2C/SPI slave interface. The M1172
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XR20M1172
64-BYTE
XR20M11721
M1172)
M1172
01-Aug-09
1152 si dlm
QFN32 pad
xr20m1172il32-f
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XRT5997IV-F
Abstract: No abstract text available
Text: XRT5997 Seven-Channel E1 Line Interface Unit November 1999-2 FEATURES The Main features are as follows: l Consists of Seven 7 Independent E1 (CEPT) Line Interface Units (Transmitter and Receiver) l Generates Transmit Output Pulses that are Compliant with the ITU-T G.703 Pulse Template
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XRT5997
048Mbps
120-Ohm
XRT59L91ID
16-lead
XRT5997IV
100-pin
XRT5997IV-F
TQFP100
01-Aug-09
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RG-62B
Abstract: RG-59B
Text: 4 T H IS D R A W IN G IS 3 U N P U B L IS H E D . R ELEASED FO R ALL C O P Y R IG H T BY TYCO E L E C T R O N IC S P U B L IC A T IO N R IG H T S - 2 , - LOC D IS T RESERVED. R EVIS IO N S 00 C O R P O R A T IO N . D E S C R IP T IO N P1 REV PER P2 RE V
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01AUG09
RG-58/U,
RG-58B/0,
RG-58C/U
RG-55/0,
RG-55B/0,
RG-223/0
RG-59B/U,
RG-62/0,
RG-62A/U,
RG-62B
RG-59B
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