0.35U Search Results

IC H 102 D6

Abstract: BL7448SM 20KHZ ISO7816 8k eeprom 1PSC 02 PSC04
Contextual Info: BL7448SM 8K 位 EEPROM 逻辑加密存 储卡电路 一概述 三、管脚描述 BL7448SM 是采用 0.35umCMOS E2PROM 工艺制造的 IC 卡用芯片 模块 。 1024 字节主存储器,带写保护功能，具有可编 程密码(PSC)。 二、特点 图 1 管脚图

CX3002

Abstract: "CHIP EXPRESS" 2308 rom CHIPX CHIP EXPRESS
Contextual Info: CX3002 0.35um CMOS ASIC Production Family available that permit options for rapid turnaround time and scalable volume production. The CX3002 product services those applications requiring ASIC performance in the networking, communications, computing, and industrial marketplace.

Contextual Info: GM71V65800C 8,388,608 WORDS x 8 BIT CMOS DYNAMIC RAM Pin Configuration Description 32 SOJ / TSOP II The GM71V65800C is the second generation dynamic RAM organized 8,388,608 words by 8 bits. The GM71V65800C utilizes 0.35um CMOS Silicon Gate Process Technology as well

Contextual Info: GM71V65400C 16,777,216 WORDS x 4 BIT CMOS DYNAMIC RAM Pin Configuration Description 32 SOJ / TSOP II The GM71V65400C is the second generation dynamic RAM organized 16,777,216 words by 4 bits. The GM71V65400C utilizes 0.35um CMOS Silicon Gate Process Technology as well

2P4M

Abstract: PMOS Embedded LOCOS
Contextual Info:
      0.35um 2P4M Embedded Flash 3.3V
     Features !
  

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Contextual Info: GM71V65400C 16,777,216 WORDS x 4 BIT CMOS DYNAMIC RAM Pin Configuration Description 32 SOJ / TSOP II The GM71V65400C is the second generation dynamic RAM organized 16,777,216 words by 4 bits. The GM71V65400C utilizes 0.35um CMOS Silicon Gate Process Technology as well

txdac

Abstract: AD975X
Contextual Info: New High Speed DAC Products February 2000 HSC Product Strategies - DAC Key Product Thrusts: ! Standard Product DACs " " " " 10/12/14 bit pin compatible TxDAC+ family development AD9750/2/4 10/12/14 bit dual port, 200MSPS, 0.35u family (AD9751/3/5) 10/12/14 bit True Dual DAC family (AD9763/5/7)

2ct10

Contextual Info: Hill ELECTRICAL CHARACTERISTICS: Inductance: 1.2mH Min @100KHz,50mV PRLSEC Turns Ratio: l:2CT@100KZ,50mV PRI DC Resistance: 0.6 Ohms Max @25°C SEC DC Resistance: 1.0 Ohms Max@25°C Interwinding Capacitance: 30pF Max @100KHz,50mV Leakage Inductance: 0.35uH Max @100KHz,50mV

CDAC10

Contextual Info: ANALOG IP BLOCK CDAC10 - CMOS 10-Bit D/A CONVERTER DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The CDAC10 is a 10-bit high-resolution high-speed CMOS digital-to-analog converter (DAC). The CDAC10 uses a segmented current steering architecture combined with a simple and fast decoding logic to achieve a very high

lvds standard

Abstract: LVDS_RX SOIC28 MA1014
Contextual Info: ANALOG IP BLOCK LVDS_RX - CMOS LVDS Receiver DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The LVDS_RX is a differential line receiver designed for applications requiring high data rates. The device supports data rates up to 622Mb/s (311 MHz). The LVDS_RX accepts (350mV) differential input signals and

Digital Frequency Doubler

Abstract: frequency doubler BW2010AGP
Contextual Info: Frequency Doubler BW2010AGP DECEMBER 1998. Ver1.0 Features General Description IN A.G.P.-2X Mode, the PLL output Frequency is . 0.35u CMOS device technology 1 133 /3Mhz which is doubled with 662/3Mhz Input . Single power supply : +3.3V Frequency. The PLL produces a good clock duty cycle with the

5045-2

Abstract: molex 5045 5045-20AG
Contextual Info: NON ACCUMULATIVE NOTES L M A T E R IA L W AFER PIN : 6 6 N Y L0 N OL9 4V-0 : D 0.635 B R A S S , GOLD(0.35umMIN.) OVER N IC KE L (2 um M IN .) P L A T IN G A T O B E A P P L I E D FOR 6CKT. AND MORE THAN 6CKT. A N O S L I T I S PR O V ID E D FOR AND L E S S THAN 5CKT.

Contextual Info: O A d va n ced P o w er Te c h n o l o g y m D APT8030JN APT8035JN O s ISOTOP* 800V 800V 27.0A 0.30Q 25.0A 0.35U 5 M " U L Recognized" File No. E145592 S POWER MOS IV« SINGLE DIE ISOTOP PACKAGE N-CHANNEL ENHANCEMENT MODE HIGH VOLTAGE POWER MOSFETS MAXIMUM RATINGS

F38h

Abstract: AD2E AD3E lcd interface with 8051 8051 pin configuration 8051 simple program Digital Clock LCD 8051 F40H Hsync Vsync generator write 8051 adc using simple program
Contextual Info: MYSON TECHNOLOGY MTV312M64 Rev 0.95 8051 Embedded Monitor Controller Flash Type with ISP FEATURES • • • • • • • • • • • • • • 8051 core, 12MHz operating frequency with double CPU clock option. 0.35uM process; 5V/3.3V power supply and I/O; 3.3V core operating.

1SV103

Contextual Info: SILICON EPITAXIAL PLANAR TYPE VARIABLE CAPACITANCE DIODE 1SV103 FM R A D IO B A N D T U N IN G APPLICATIONS. • • Low Series Resistance : rs = 0.35U Typ.; Small Package. M A X IM U M RATINGS (Ta = 25°C CHARACTERISTIC Reverse Voltage Junction Tem perature

35L004003216

Contextual Info: NexFlash Technologies, Inc. CONFIDENTIAL Preliminary Specification 35L004003216 Specification, Revision - Embedded High Speed NexFLASH Memory 35L004003216 Low Power 512K-bit 32K x 16 Embedded FN-FN FLASH Memory Features • FN-FN FLASH Technology • 0.35um, 3-well CMOS Technology

35C00312816

Contextual Info: NexFlash Technologies, Inc. CONFIDENTIAL ADVANCE INFORMATION Embedded High Speed NexFLASH Memory 35C00312816 High Speed 2-Mbit Embedded FN-FN FLASH Memory Features • FN-FN FLASH Technology • 0.35um, 3-well CMOS Technology • Single 2.7 – 3.6V Supply

metal detector diagram loop

Abstract: metal detector circuit diagram metal detector diagram
Contextual Info: HD3PLO3 3.3V Fixed PLL Ver.l.O updated in May 24, 2OOO HD3PLO3(3.3V Fixed PLL) General Description The HD3PL03 is a 3.3 V CMOS Analog Phase Locked Loop (PLL) clock generator. This PLL is suitable for very low power portable application using H EI’s standard 0.35um Single poly Triple metal ASIC Process.

2P4M

Abstract: 4560
Contextual Info:
      0.35um 2P4M Mixed Signal 3.3V / 5V
     Features ! ! ! ! ! ! ! ! ! !
                  !    !"

cmos transistor 0.35 um

Abstract: 0.35Um c035 ZENER C035 5V IMD2 transistor bsim3v3 polysilicon 20v zener diode 3.3v zener C035
Contextual Info: 0.35µ µm 5V / 3.3V CMOS Process ID: SL [C035] Applications Main Process Flow • Interfacing high density industry- • P Substrate standard 0.35um core logic to 5V • LOCOS Field Oxidation

SCADC10

Contextual Info: ANALOG IP BLOCK SCADC10 - CMOS 10-Bit A/D CONVERTER DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The SCADC10 is a complete analog to digital converter cell which operates from a single supply. It performs sampling, analog-to-digital conversion, generating a

F100K

Abstract: SOIC28 transmitter 446 mhz Analog Delay Lines
Contextual Info: ANALOG IP BLOCK PECL_TX - CMOS PECL Transmitter PROCESS C35B3 0.35um DATA SHEET DESCRIPTION The PECL_TX is a differential 3.3 V PECL transmitter featuring a transmission speed of 622 Mb/s with standard F100K levels (referred to the positive supply). Unlike other

myson isp

Abstract: MTV312M64 F42H Hsync Vsync generator myson 312m 24LC02 8051 simple lcd program 24Lc02 eeprom
Contextual Info: MYSON TECHNOLOGY MTV312M64 Rev 0.99 8051 Embedded Monitor Controller Flash Type with ISP FEATURES • • • • • • • • • • • • • • • 8051 core, 12MHz operating frequency with double CPU clock option 0.35uM process; 5V/3.3V power supply and I/O; 3.3V core operating

ADC1220

Abstract: MS 1117 ADC EN16 AD711 AD8138
Contextual Info: ANALOG IP BLOCK ADC1220 - CMOS 12-Bit Pipelined A/D CONVERTER DATA SHEET PROCESS DESCRIPTION C35B3 0.35um The ADC1220 is a high-speed pipeline ADC core cell achieving sampling rates up to 20 MS/s. A S/H circuit is built-in to provide low jitter noise and a fully differential