0.13UM ST Search Results

0.13UM ST Result Highlights (5)

Part	Manufacturer	Description
X9313UMZT1	Renesas Electronics Corporation	Digitally Controlled Potentiometer (XDCP™), Linear, 32 Taps, 3 Wire Interface, Terminal Voltages ± VCC
X9313UMIZ-3T1	Renesas Electronics Corporation	Digitally Controlled Potentiometer (XDCP™), Linear, 32 Taps, 3 Wire Interface, Terminal Voltages ± VCC
X9313UMIZ-3	Renesas Electronics Corporation	Digitally Controlled Potentiometer (XDCP™), Linear, 32 Taps, 3 Wire Interface, Terminal Voltages ± VCC
X9313UMZ-3T1	Renesas Electronics Corporation	Digitally Controlled Potentiometer (XDCP™), Linear, 32 Taps, 3 Wire Interface, Terminal Voltages ± VCC
X9313UMZ	Renesas Electronics Corporation	Digitally Controlled Potentiometer (XDCP™), Linear, 32 Taps, 3 Wire Interface, Terminal Voltages ± VCC

0.13UM ST Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
ARM9TDMI Abstract: ARM1020E samsung hdd Samsung S ARM teaklite DSPG SMART ASIC bga ARM920t datasheet Avant Electronics USB samsung Text: V S MSUNG STDH150 ELECTRONICS STDH150 Standard Cell 0.13um System-On-Chip ASIC Dec 2001, V1.0 Features Analog cores - Ldrawn = 0.13um 1.2/2.5/3.3V Device - Up to 34.3 million gates - Power dissipation:9nW/MHz@1.2V, 2SL, ND2 3.3/5.0V - Gate Delay: 52ps @ 1.2V, 2SL, ND2	Original	STDH150 STDH150 ARM920T/ARM940T, ARM9TDMI ARM1020E samsung hdd Samsung S ARM teaklite DSPG SMART ASIC bga ARM920t datasheet Avant Electronics USB samsung	PDF
ARM dual port SRAM compiler Abstract: DSPG teaklite ARM9TDMI ARM1020E samsung hdd UART 16C450 Standard Cell 0.13um System-On-Chip ASIC ARM920T ARM926EJ Text: V S MSUNG STD150 ELECTRONICS STD150 Standard Cell 0.13um System-On-Chip ASIC Oct 2001, V1.0 Features Analog cores - Ldrawn = 0.13um 1.2/2.5/3.3V Device - Up to 46 million gates - Power dissipation:9nW/MHz@1.2V, 2SL, ND2 3.3/5.0V - Gate Delay: 52ps @ 1.2V, 2SL, ND2	Original	STD150 STD150 ARM920T/ARM940T, ARM dual port SRAM compiler DSPG teaklite ARM9TDMI ARM1020E samsung hdd UART 16C450 Standard Cell 0.13um System-On-Chip ASIC ARM920T ARM926EJ	PDF
ternary content addressable memory VHDL Abstract: ARM1020E SMART ASIC bga ARM dual port SRAM compiler Samsung ASIC 0.13um standard cell library Standard Cell 0.13um System-On-Chip ASIC DSPG samsung lcd JTAG "content addressable memory" precharge Text: V S MSUNG STDL150 ELECTRONICS STDL150 Standard Cell 0.13um System-On-Chip ASIC March 2003, V2.0 Features Analog cores - Ldrawn = 0.13um 1.5/2.5/3.3V Device 1.5/2.5/3.3V - Up to 45.8 million gates Interface - Power dissipation: 13nW/MHz@1.5V, 2SL, ND2 5.0V	Original	STDL150 STDL150 13nW/MHz ARM920T/ARM940T, ternary content addressable memory VHDL ARM1020E SMART ASIC bga ARM dual port SRAM compiler Samsung ASIC 0.13um standard cell library Standard Cell 0.13um System-On-Chip ASIC DSPG samsung lcd JTAG "content addressable memory" precharge	PDF
VCO 10GHz Abstract: tsmc cmos TSMC 0.13um CMOS 10GHz clock oscillator XCVR 10gbps clock and data recovery 10GHz VCO applications of prbs generator 10Gbps P802 Text: SB3000 PRODUCT BRIEF SILICON BRIDGE SB3000 - 10Gbps Serial Low Power 0.13um TSMC CMOS Programmable Transceiver Macro Cell FEATURES • Power dissipation: 400mW typical • Available in 0.13um TSMC CMOS technology • Compliant with 10Gbps Ethernet IEEE P802.3ae,	Original	SB3000 SB3000 10Gbps 400mW 32/64-bit 10GHz s/622MHz VCO 10GHz tsmc cmos TSMC 0.13um CMOS 10GHz clock oscillator XCVR 10gbps clock and data recovery 10GHz VCO applications of prbs generator P802	PDF
ARM1020E Abstract: samsung hdd Samsung Soc processor 4468 8 pin ARM920t datasheet ARM9TDMI DSPG ARM SRAM compiler UART 16C450 ARM940T Text: V S MSUNG STD150 ELECTRONICS STD150 Standard Cell 0.13um System-On-Chip ASIC Oct 2001, V1.0 Features Analog cores - Ldrawn = 0.13um 1.2/2.5/3.3V Device - Up to 46 million gates - Power dissipation:9nW/MHz@1.2V, 2SL, ND2 3.3/5.0V - Gate Delay: 52ps @ 1.2V, 2SL, ND2	Original	STD150 STD150 ARM920T/ARM940T, ARM1020E samsung hdd Samsung Soc processor 4468 8 pin ARM920t datasheet ARM9TDMI DSPG ARM SRAM compiler UART 16C450 ARM940T	PDF
PLL2113X Abstract: 50MHz-300MHz Text: 50MHz ~ 300MHz FSPLL PLL2113X Ver 1.0.1. Aug. 2002 GENERAL DESCRIPTION FEATURES • 0.13um CMOS device technology The pll2113x is a Phase Locked Loop (PLL) frequency synthesizer. The PLL provides frequency multiplication capabilities. The output clock frequency	Original	50MHz 300MHz PLL2113X pll2113x 300MHz 150ps 50MHz 50MHz-300MHz	PDF
PLL2108X Abstract: No abstract text available Text: 50MHz ~ 300MHz FSPLL PLL2108X Ver 1.3.0. May. 2002 GENERAL DESCRIPTION FEATURES • 0.13um CMOS device technology The pll2108x is a Phase Locked Loop (PLL) frequency synthesizer. The PLL provides frequency multiplication capabilities. The output clock frequency	Original	50MHz 300MHz PLL2108X pll2108x 300MHz 150ps 50MHz	PDF
0.18-um Abstract: 0.35uM STI CS100A CS70DL CS-80 pMOS NAND GATE 0.35Um CS70B Fujitsu inverter CG61 Text: CMOS PROCESS TECHNOLOGY 11 fujitsu-fme.com FUJITSU MICROELECTRONICS EUROPE www.fujitsu www.fujitsu fme.com ASIC & COT TECHNOLOGY ROADMAP Node 0.25um 0.18um CS70B 0.10um CS70DLS CS80DL 0.2 L gate [mm] CS70DL 0.13um CS80/CS80A ASIC/DRAM Half Pitch CS90A MPU	Original	CS70B CS70DL CS70DLS CS80DL CS80/CS80A CS90A CS100 CS90DLS CS100A/DL 0.18-um 0.35uM STI CS100A CS-80 pMOS NAND GATE 0.35Um CS70B Fujitsu inverter CG61	PDF
PLL2124X Abstract: No abstract text available Text: 50MHz ~ 300MHz FSPLL PLL2124X Ver 1.0.0. July, 2002 GENERAL DESCRIPTION FEATURES • 0.13um CMOS device technology The pll2124x is a Phase Locked Loop (PLL) frequency synthesizer. The PLL provides frequency multiplication capabilities. The output clock frequency	Original	50MHz 300MHz PLL2124X pll2124x 300MHz 150ps 50MHz	PDF
Untitled Abstract: No abstract text available Text: QUALIFICATION REPORT Date: 3/28/12 QUALITY ENG : PART NUMBER MICREL QA/REL KSZ8864RMN/RMNI/RMNU Qual vehicles PACKAGE TYPE : ASSEMBLY FAB LOC PROCESS 64L MLF QFN TICP DONGBU, TAIWAN 0.13um KSZ8864RMNU QUALIFICATION RESULTS: Test # Reference Test Conditions	Original	KSZ8864RMN/RMNI/RMNU KSZ8864RMNU JESD22 AEC-Q100008 AEC-Q100002 AEC-Q100001 Mil-STD883	PDF
PLL2127X Abstract: 100MHz FREQUENCY DIVIDER Text: 20MHz ~ 100MHz FSPLL PLL2127X Ver 0.0 GENERAL DESCRIPTION FEATURES • 0.13um CMOS device technology The pll2127x is a Phase Locked Loop PLL frequency synthesizer. The PLL provide frequency multiplication capabilities. The output clock frequency FOUT is related to the input clock frequency FIN by	Original	20MHz 100MHz PLL2127X pll2127x 100MHz 200ps 20MHz 100MHz FREQUENCY DIVIDER	PDF
PLL2126X Abstract: No abstract text available Text: 20MHz ~ 100MHz FSPLL PLL2126X Ver 0.0 GENERAL DESCRIPTION FEATURES • 0.13um CMOS device technology The pll2126x is a Phase Locked Loop PLL frequency synthesizer. The PLL provide frequency multiplication capabilities. The output clock frequency FOUT is related to the input clock frequency FIN by	Original	20MHz 100MHz PLL2126X pll2126x 100MHz 200ps 20MHz	PDF
vco 27MHz Abstract: PLL VCO 27MHz phase sequence detector phone tap Text: 0.13um, 12-145 MHz Phase Locke d Loop FEATURES • Industry Standard 0.13 Micron CMOS ■ Digital Logic Process; 1.2/3.3 volts ■ Digital Controlled Output Frequency — up to 145 MHz with a Symmetric Duty Cycle ■ Embedded VCO Frequency Range: 216 MHz, locked to 27	Original		PDF
TSMC 0.13um CMOS Abstract: "programmable on-chip termination" 10gbps serdes tsmc cmos XCVR CHIP EXPRESS SB1011 ethernet mdio circuit diagram mdio termination Text: SB1011 PRODUCT BRIEF SILICON BRIDGE SB1011 - Quad 0.625 - 4.25Gbps Low Power CMOS Transceiver Macro Cell in 0.13um TSMC Process FEATURES BENEFITS/ADVANTAGES • • • • • • • • • • • • • • • Quad SerDes transceivers with Clock multiplier and	Original	SB1011 SB1011 25Gbps 0625Gbps, 125Gbps, 25Gbps, 10b/20b TSMC 0.13um CMOS "programmable on-chip termination" 10gbps serdes tsmc cmos XCVR CHIP EXPRESS ethernet mdio circuit diagram mdio termination	PDF

calmRISC16 Abstract: S3FC9 scrambling "flash controller" smart card 7816 emv 7816 smart card Text: S3FC9CE 1 Bank Flash Embedded Smart Card Controller Advanced Information Publication Number: 00-S3-FC9CE Feb 2007 rev2 ) OVERVIEW The S3FC9CE is high performance security controller is specially designed and packaged for "Smart Card" application and fabricated using a secured 0.13um CMOS technology. The CalmRISC16 16-bit CPU and secure	Original	00-S3-FC9CE CalmRISC16 16-bit CalmRISC16) 84Kbyte 176Kbyte 16-Bits S3FC9 scrambling "flash controller" smart card 7816 emv 7816 smart card	PDF
PLL2128X Abstract: No abstract text available Text: 20MHz ~ 100MHz FSPLL PLL2128X Ver 0.0 GENERAL DESCRIPTION FEATURES • 0.13um CMOS device technology The pll2128x is a Phase Locked Loop PLL frequency synthesizer. The PLL provide frequency multiplication capabilities. The output clock frequency FOUT is related to the input clock frequency FIN by	Original	20MHz 100MHz PLL2128X pll2128x 100MHz 200ps 20MHz	PDF
Pseudo SRAM Abstract: No abstract text available Text: Low Power Pseudo SRAM 4 M Words x 16 bit CS26LV64163 Revision History Rev. No. History Issue Date 1.0 Initial issue Jan.19, 2007 1.1 Upgrade wafer process from 0.13um to 90nm Dec. 18, 2009 1 Rev 1.1 Chiplus reserves the right to change product or specification without notice.	Original	CS26LV64163 CS26LV64163 150uA 200us Pseudo SRAM	PDF
S3FS9 Abstract: arm7 architecture calculator circuit diagram ARM SC100 Architecture S3FS ARM SC100 ARM SC100 7816 S3FS92F CRC calculator S3FS92 Text: S3FS92F 1 Bank Flash Embedded Smart Card Controller Advanced Information Publication Number: 00-S3-FS92F Mar 2007 rev1 OVERVIEW The S3FS92F is a cost-effective, high performance security controller designed and packaged for "Smart Card" application and using a secured 0.13um Flash technology. The 16-/32-bit SC100 RISC CPU and secure flash	Original	S3FS92F 00-S3-FS92F S3FS92F 16-/32-bit SC100 SC100 32-bit 256kB 16-Bit S3FS9 arm7 architecture calculator circuit diagram ARM SC100 Architecture S3FS ARM SC100 ARM SC100 7816 CRC calculator S3FS92	PDF
CS26LV64163 Abstract: cs26lv64163 data Text: Low Power Pseudo SRAM 4 M Words x 16 bit CS26LV64163 Revision History Rev. No. History Issue Date 1.0 Initial issue Jan.19, 2007 1.1 Upgrade wafer process from 0.13um to 90nm Dec.18, 2009 1.2 Add the package dimensions: D2 and E2 Aug.26, 2010 1 Rev 1.2 Chiplus reserves the right to change product or specification without notice.	Original	CS26LV64163 CS26LV64163 cs26lv64163 data	PDF
1016w Abstract: A15F6 Text: New Products MBM29BS12DH 128Mbit x16 Burst Mode Flash Memory MBM29BS12DH A Flash Memory mounted with burst mode, operated on a single 1.8V power supply. Adoption of an original FUJITSU sensing method reduces the current consumption to one-twentieth the standard level of competitor	Original	MBM29BS12DH 128Mbit 128M-bit 40REF 80REF 1016w A15F6	PDF
FBGA-60 Abstract: FBGA60 fbga60 package Text: New Products MBM29BS64LF 64M-bit x16 Burst Mode Flash Memory MBM29BS64LF FUJITSU has developed a new burst mode flash memory device operating with a 1.8 V single power supply. This device incorporates an original FUJITSU sense system that reduces the current consumption (mean value in the standby mode)	Original	MBM29BS64LF 64M-bit 64M-bit fMBM29BSxxx 128M-bit MBM29BS64LF, FBGA-60 FBGA60 fbga60 package	PDF
0.18-um Abstract: No abstract text available Text: Serial LINK Code Information 1/2 S5SXXXXXXX - XXXX 1 2 3 4 5 6 7 8 1. System LSI (S) 9 10 11 12 13 14 15 9. Interface (Serial / Parallel) 4 : 4 bit interface 5 : 5 bit interface 8 : 8 bit interface 1 : 10 bit interface 6 : 16 bit interface 2 : 20 bit interface	Original		PDF
LBC7 Abstract: BiCD 0.13 BCD8 0.18um LDMOS BCD8* riccardi cd013 BCD8 st 7to30V LBC7 RONA free transistor e2p Text: Ultra-low On-Resistance LDMOS Implementation in 0.13 m CD and BiCD Process Technologies for Analog Power IC's Koji Shirai, Koji Yonemura, Kiminori Watanabe, Koji Kimura System LSI Division, Toshiba Semiconductor Company, 2-5-1 Kasama, Sakae, Yokohama, Kanagawa/Japan,	Original	7to30V LBC7 BiCD 0.13 BCD8 0.18um LDMOS BCD8* riccardi cd013 BCD8 st LBC7 RONA free transistor e2p	PDF
internal block diagram of mobile phone Abstract: s3c2413 touch screen controller samsung ARM926EJ camera interface samsung OneNAND Samsung sd ARM926EJ-S AMBA APB UART touch screen controller for mobile phone Text: Samsung S3C2413 Mobile Processor Cost-effective Solution for Smartphones and Other Handhelds The Samsung S3C2413 mobile processor gives designers of products such as smartphones, portable GPS devices and PDAs a solution for reducing system costs while providing	Original	S3C2413 S3C2413 16/32-bit ARM926EJ-S DS-07-SLSI-002 internal block diagram of mobile phone touch screen controller samsung ARM926EJ camera interface samsung OneNAND Samsung sd AMBA APB UART touch screen controller for mobile phone	PDF

0.13UM ST Search Results

0.13UM ST Result Highlights (5)

0.13UM ST Datasheets Context Search

ARM9TDMI

ARM dual port SRAM compiler

ternary content addressable memory VHDL

VCO 10GHz

ARM1020E

PLL2113X

PLL2108X

0.18-um

PLL2124X

Untitled

PLL2127X

PLL2126X

vco 27MHz

TSMC 0.13um CMOS

calmRISC16

PLL2128X

Pseudo SRAM

S3FS9

CS26LV64163

1016w

FBGA-60

0.18-um

LBC7

internal block diagram of mobile phone